GLOBALFOUNDRIES Announces Availability of Embedded MRAM on Leading 22FDX® FD-SOI Platform September 20, 2017Advanced embedded non-volatile memory solution delivers ‘connected intelligence’ by expanding SoC capabilities on the 22nm process node Santa Clara, Calif., September 20, 2017 — GLOBALFOUNDRIES today announced the availability of its scalable, embedded magnetoresistive non-volatile memory (eMRAM) technology on the company’s 22nm FD-SOI (22FDX®) platform. As the industry’s most advanced embedded memory solution, GF’s 22FDX eMRAM provides high performance and superior reliability for broad applications in consumer and industrial controllers, data centers, Internet of Things (IoT), and automotive. As recently demonstrated, GF’s 22FDX eMRAM features the ability to retain data through 260°C solder reflow, while maintaining an industry-leading eMRAM bitcell size that retains data for more than 10 years at 125°C, enabling the technology to be used for general purpose, industrial, and automotive microcontroller units (MCUs). The power efficiency of FDX™ and eMRAM, coupled with the available RF connectivity and mmWave IP, makes 22FDX an ideal platform for battery-powered IoT and autonomous vehicle radar system-on-chips (SoCs). “Customers are seeking to expand their product capabilities as an increasing number of applications require a high-performance, non-volatile memory solution,” said Dave Eggleston, vice president of Embedded Memory at GF. “We are excited to release 22FDX eMRAM, a high reliability embedded memory technology that provides system designers with the versatility to build greater functionality into their MCUs and SoCs, while enhancing performance and power efficiency.” The high reliability and superior scalability of GF’s eMRAM makes it a cost effective option at advanced process nodes for multiple markets. Moreover, the versatility of GF’s eMRAM enables fast write performance and high endurance, allowing it to be used for both code storage and working memory. The availability of GF’s 22FDX eMRAM is a result of the company’s multi-year partnership with Everspin Technologies. The partnership has already demonstrated and sampled 1Gb DDR MRAM chips, and productized 256Mb DDR MRAM chips, products which are available exclusively from Everspin. Process design kits for 22FDX eMRAM and RF solutions are available now. Customer prototyping of 22FDX eMRAM on multi-project wafers (MPWs) is on track for the first quarter of 2018, with risk production planned by the end of 2018. Custom eMRAM design services are available today from GF and our design partners, including eMRAM macros ranging from 2Mb to 32Mb, featuring easy design-in eFlash and SRAM interface options. Customers interested in learning more about GF’s 22FDX eMRAM solution, contact your GLOBALFOUNDRIES sales representative or go to www.globalfoundries.com. ABOUT GF GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. GLOBALFOUNDRIES is owned by Mubadala Investment Company. For more information, visit https://www.globalfoundries.com. Contacts: Erica McGillGF(518) 305-5978[email protected]
GLOBALFOUNDRIES Introduces New 12nm FinFET Technology for High-Performance Applications September 20, 2017New 12LP technology offers density and performance improvement over current generation Platform features enhancements for next-gen automotive electronics and RF/analog applications Santa Clara, Calif., Sept. 20, 2017 – GLOBALFOUNDRIES today announced plans to introduce a new 12nm Leading-Performance (12LP) FinFET semiconductor manufacturing process. The technology is expected to deliver better density and a performance boost over GF’s current-generation 14nm FinFET offering, satisfying the processing needs of the most demanding compute-intensive applications from artificial intelligence and virtual reality to high-end smartphones and networking infrastructure. The new 12LP technology provides as much as a 15 percent improvement in circuit density and more than a 10 percent improvement in performance over 16/14nm FinFET solutions on the market today. This positions 12LP to be fully competitive with other 12nm FinFET foundry offerings. The technology leverages GF’s expertise at Fab 8 in Saratoga County, N.Y., where its 14nm FinFET platform has been in high-volume production since early 2016. “The world is in the midst of an unprecedented transition to an era of connected intelligence,” said GF CEO Sanjay Jha. “This new 12LP technology provides the performance and density improvements necessary to help our customers continue innovating at the system level, as they deliver real-time connectivity and edge processing to everything from high-end graphics and automobiles to industrial applications.” “We are pleased to extend our longstanding relationship with GLOBALFOUNDRIES as a lead customer for their new 12LP technology,” said Mark Papermaster, CTO and senior vice president of technology and engineering, AMD. “Our deep collaboration with GF has helped AMD bring a set of leadership high-performance products to market in 2017 using 14nm FinFET technology. We plan to introduce new client and graphics products based on GF’s 12nm process technology in 2018 as a part of our focus on accelerating our product and technology momentum.” In addition to transistor-level enhancements, the 12LP platform will include new market-focused features specifically designed for automotive electronics and RF/analog applications—two of the fastest-growing segments in the industry. Emerging automotive applications in vehicle safety and automated driving require a combination of processing power and extreme reliability. The 12LP platform delivers both, with plans for Automotive Grade 2 qualification at Fab 8 by Q4 2017. A new RF offering extends the 12LP platform for RF/analog applications such as premium-tier transceivers in sub-6GHz wireless networks. 12LP offers the best scaling in both logic and memory for RF chip architectures with primarily digital and less RF/analog content. GF’s new 12nm FinFET technology complements its existing 12nm FD-SOI offering, 12FDXTM. While some applications require the unsurpassed performance of FinFET transistors, many connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve. 12FDX provides an alternative path for the next generation of connected intelligent systems, enabling the performance of 10nm FinFET with better power consumption, lower cost, and better RF integration than current-generation foundry FinFET offerings. About GF: GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. GLOBALFOUNDRIES is owned by Mubadala Investment Company. For more information, visit https://www.globalfoundries.com. Contacts: Erica McGillGF(518) 795-4250[email protected]
Synopsys和格芯合作开发用于22FDX®工艺的DesignWare IP September 20, 2017Synopsys, Inc. (Nasdaq: SNPS) today announced its collaboration with GLOBALFOUNDRIES (GF) to develop DesignWare® IP.
Synopsys设计平台获得格芯的22FDX工艺技术认证 September 20, 2017Synopsys, Inc. (Nasdaq: SNPS) today announced that GLOBALFOUNDRIES (GF) has certified the Synopsys Design Platform for the GF 22nm FD-SOI (22FDX™) process, ensuring designers achieve optimized…
Embedded FPGAs from Menta qualified for GLOBALFOUNDRIES’® Advanced 14nm FinFET and 32nm SOI Process Technologies September 19, 2017Montpellier, France – September 19, 2017 – Menta today announced that its embedded FPGA (eFPGA) IP is fully qualified for GLOBALFOUNDRIES’ (GF) advanced 14nm FinFET and 32nm SOI process technologies.
来自Menta的嵌入式FPGA获得格芯先进的14纳米FinFET和32纳米SOI工艺技术认证 September 19, 2017Embedded FPGAs from Menta qualified for GLOBALFOUNDRIES’® Advanced 14nm FinFET and 32nm SOI Process Technologies eFPGAs enable built-in programmability in SoCs targeting defense, aerospace, ADAS, IoT and data center applications
GLOBALFOUNDRIES Announces Enhanced RF SOI Process Design Kit For Use with CWS’ SiPEX™ Design Solution September 18, 2017Enhanced PDK incorporates design productivity tool to further enhance high-performance RF SOI switches Santa Clara, Calif., September 18, 2017 — GLOBALFOUNDRIES today announced the availability of a new set of enhanced RF SOI process design kits (PDKs) to help designers improve their designs of RF switches and deliver differentiated RF front-end solutions for a wide range of markets including front-end modules for mobile devices, mmWave, 5G and other high-frequency applications. GF’s advanced RF technology platform, 7SW SOI, is optimized for multi-band RF switching in next-generation smartphones and poised to drive innovation in Internet of Things (IoT) applications. Designed for use with Coupling Wave Solutions’ (CWS) simulation tool, SiPEX™, GF’s 7SW SOI PDK allows designers to integrate RF switches with other critical RF blocks that are essential to the design of complex electronic systems for future RF communication chips. Specifically, this new capability allows designers to improve RF simulation output by simulating a highly-resistive substrate parasitic effect across their entire design. “GF leads the industry in RFSOI technology, and we are committed to providing our customers with design productivity solutions for our RF processes,” said Bami Bastani, senior vice president of RF at GF. “CWS’ SiPEX™ tool provides our customers with best-in-class correlation between simulated results and real world measurements, further optimizing the design layout to achieve efficiency and deliver differentiated RF front-end solutions.” “This is great news for the RF design community,” said Brieuc Turluche, chairman of the board of directors and chief executive officer of CWS. “The integration of SiPEX into GF’s RF SOI PDKs is a major milestone to achieve first-time correct complex and optimized RF SOI designs for high-performing cellular, IoT, 5G and Wi-Fi communication chips.” GF’s RF SOI technologies offer significant performance, integration and area advantages in front-end RF solutions for mobile devices and RF chips for high-frequency, high-bandwidth wireless infrastructure applications. CWS’ SiPEX accelerates the design of RF SOI switches by improving linearity simulation accuracy. It can also be effective in the design of low-noise amplifiers (LNA) and power amplifiers (PA), enabling designers to reduce their size to lower costs SiPEX™ is available in the current release of GF’s 7SW SOI PDK. For more information on the company’s RF SOI solutions, contact your GF sales representative or go to www.globalfoundries.com. About CWS CWS is the leader in system-level interference analysis of complex designs incorporating RF and analog blocks. Currently, CWS offers two products: WaveIntegrity™ and SiPEX™. Based on a unique harmonic analysis approach, WaveIntegrity™ is used by chip architects and designers to drive the chip design floorplanning. It is also used by package and PCB designers to integrate the noise-related design constraints in the final chip operational environment. SiPEX™, already included in TowerJazz’s CS18 and STM’s H9 SOI FEM Process Design Kits, improves the linearity of RF SOI designs and accurately models and simulates critical RF functions for 5G and IoT communications. Founded in 2005, CWS’ offices are located in Paris, Grenoble, France and San Jose, CA, USA. More information about the company, its products, and services is available at www.cwseda.com. About GF: GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. GLOBALFOUNDRIES is owned by Mubadala Investment Company. For more information, visit https://www.globalfoundries.com. Contacts: Erica McGillGLOBALFOUNDRIES(518) 305-5978[email protected]
网络应用的2.5D到来 August 30, 2017作者: Dave Lammers 面对带宽问题,网络公司正在转向转接板、HBM2 DRAM和先进ASIC技术。 当大网络公司开始开发新一级别的兆兆位路由器时，他们都来到了一个“临界点”，“临界点”概念是由The Linley Group的网络分析师Bob Wheeler提出的。 Cisco, Juniper, Nokia, 以及其他大公司在努力从层叠印制电路板DR DRAM中取得足够带宽的同时, 已经发现了针脚数目爆炸式的增长。 网络客户现已可使用由格芯提供的全新14纳米ASIC (FX-14™) 方案，此方案提供载于硅转接板上的高带宽内存(HBM2)链接。Rambus Inc. 公司(位于森尼维尔) 与格芯工程师合作，将 Rambus PHY 整合至 FX-14 ASIC 平台，提供了令人叹为观止的 每秒2 (Tb/s) 的带宽。 “外置内存无法跟上ASIC缓冲的带宽需求，这是已预见的问题，而这就是本问题的解决办法，” Wheeler 说道。 “人们尝试尽可能地使用通用型 DRAM，但是由于针脚数目的爆发式增长，现在我们正面临着一个临界点。” 通讯类ASIC的市场大概为十亿美元，Wheeler 提到, 而路由器是十分昂贵的系统，足以支持转接板 (2.5D) 方案满足高速数据缓冲的成本。 对于层叠PCB上的DDR型DRAM来说，Wheeler 声称 “ASIC的主要问题来自针脚数。设备的针脚数甚至可高达2000。HBM的魅力在于它具备通用的接口，并且包括在封装内一体化提供，无需寻求额外的接口。” 网络以外的市场? 取决于成本是否可以降低， 2.5D (转接板)方案可用于其他应用例如数据处理、高端图像、自动驾驶车辆、人工智能和其他高带宽类方案，格芯封装研发部、业务技术营运部副总裁 Dave McCann如此说道。 向转接板技术转移在排线密度上带来了巨大的进步。对于层叠PCB方案来说，连接线和线之间的空隙为12微米，可是由于垂直过孔50微米是不可取的，大量的空间被浪费在绕过或避免垂直过孔，通常连线密度无法达到理想值。有了硅转接板的帮助，连接线及空隙可达到逻辑芯片背板的级别，约为0.8微米，格芯技术开发高级经理Walter Kocon说道。 要在PHY和HBM2内存间使用逻辑级别的排线，需要依靠包括了光刻在内的晶元级工具。由于转接板比传统芯片更大，多处区域需被拼接在一起。但是 Kocon声称现下的分档器在刻线切换能力上非常出色，在创造更大转接板的道路上也取得了长足进展。 晶元长的工具比传统层叠制程工具要更昂贵，但是回报也同样巨大-芯片上的I/O可高达约1700个。正如McCann提到的，缩小单段排线的距离可将功耗保持在可控制范围，而这是目前仍在使用的层叠序列接口无法做到的。 全方位应用无死角 “由于晶元制造技术(小于1微米)在转接板中的应用,过孔技术得以实现,0.8微米排线和间隙可以在多个层面得到实现,而从根本上来说,并没有过孔无法应用的死角。对于传统PCB来说,排线必须从ASIC引入再回到DIMM卡上,浪费了能源与时间,”McCann说道。而基于转接板的内连接在数量级上更小，设备间的距离只有数百微米，大量的平行排线密度足以支持多兆兆位级别的带宽。 可是在转接板技术上存在制造难题。 “转接板和ASIC本身的尺寸很大。首先，我们必须创造ASIC和转接板之间的接口。拓展属性的匹配是创造合适接口的关键之一。控制扭曲的设计和集成处理尤为重要。将压力均匀散布于转接板和位于其下的叠层也十分重要，否则接口将存在巨大误差。” McCann 说道。 转接板和ASIC之间十分靠近，而焊锡凸块大约为70微米，在这个前提下，控制扭曲是增加2.5D技术产量的关键因素。 “这意味着产品对于扭曲的容忍性将极为有限，” McCann 说道。被推向一起的焊锡或被向反方向拉扯的焊锡将带来链接上的问题。 “我们要求制造加工保证所有分层都为平面，但我们相信在OSAT合作伙伴的帮助下，我们可以满足这个要求。” McCann 说道。 PHY合作 PHY是另一个技术难题，这个难题已被 Rambus和格芯一同克服。 Frank Ferro是Rambus产品市场部高级主管，他解释说，HBM2 PHY是一个混合信号功能，必须针对每个制程节点进行精确设计。 “我们进行了大量的信道建模，并设计了满足各种要求的PHY。而这些都是通过合作开发完成的。我们对于整个制程进行了许多讨论，以确保设计的稳定。项目伊始，让设计成功实现，就是Rambus的（建模和信号完整性）工具和参与到设计这些PHY的所有工程师的目标。” DDR DRAM支持72数位的带宽，而HBM2支持1024位。1024数位的信号完整性控制极具挑战性，Ferro向格芯工程师们寻求帮助，指望于他们从IBM微电子部门带来的高速信号经验。 当被问及2.5D方案是否将占领整个行业的高速部分，Ferro称这将取决于制造的产量以及HBM2 DRAM的成本减少。 “2.5D 必须经由大批量制造的考验。这是硅技术中极大的一部分，扭曲必须得到控制。” Tad Wilder是格芯技术员工的高级成员, 他声称2兆兆位每秒的带宽“对于单一核心来说是令人叹为观止的。而总共可放置4块HBM2 PHY的芯片，将为ASIC设计者带来前所未有的8兆兆位每秒的带宽，并具备低功耗低延迟DRAM。”他补充道14纳米 HBM PHY “是我们为ASIC生产过最大的核心，其包含15000外置针脚可接至内存控制器、1700外置针脚可接至转接板各层DRAM的基本晶体。” 每一层DRAM都包含一个基础晶体，与ASIC的HBM2 PHY以及另外高达8个不同叠层的基础晶体进行沟通，链接通过数千个垂直硅过孔（TSV）实现。每层HBM DRAM的总内存可高达32GB。为了减少1000个输入输出开关的噪音信号，ASIC HBM2 PHY可以利用8个128数位信号通道的完全独立性，并通过对每个信号通道的相应时序控制调整来实现。 Linley Group分析师 Wheeler见证了HBM2标准建立所带来的趋势。Hynix是最初的发起者，可是 Wheeler说 Samsung已具备自己的HBM2并愈发强势。由于方案的成本大部分来自于HBM2内存，多个HBM2供应商间将展开激烈竞争，提高产量、降低成本并优化性能。 当被问及是否认为2.5D方案将进一步普及，McCann说 “这是本时代一个非常伟大的技术，并能带来巨大的回报。问题是，我们是否能降低成本并提高产量？” 关于作者 Dave Lammers是固态技术特约撰稿人，也是格芯的Foundry Files的特约博客作者。他于20世界80年代早期在美联社东京分社工作期间开始撰写关于半导体行业的文章，彼时该行业正经历快速发展。他于1985年加入E.E. Times，定居东京，在之后的14年内，足迹遍及日本、韩国和台湾。1998年，Dave与他的妻子Mieko以及4个孩子移居奥斯丁，为E.E Times开设德克萨斯办事处。Dave毕业于美国圣母大学，获得密苏里大学新闻学院新闻学硕士学位。
2.5D Arrives for Networking Applications August 22, 2017By: Dave Lammers Faced with bandwidth issues, networking companies are turning to interposers, HBM2 DRAM and leading-edge ASIC technology. When the big networking companies began developing a new class of terabit routers, they reached what Bob Wheeler, networking analyst at The Linley Group, calls “the breaking point.” These companies — Cisco, Juniper, Nokia, and others — had been watching the pin counts on their router ASICs “explode” as they worked to get enough bandwidth from commodity DDR DRAMs, mounted on laminate printed circuit boards. Networking customers are now able to use a new 14nm ASIC (FX-14™) solution from GLOBALFOUNDRIES® which offers connections to High-Bandwidth Memory (HBM2) mounted on a silicon interposer. Rambus Inc. (Sunnyvale) and GF engineers cooperated to bring a Rambus PHY to the FX-14 ASIC platform that provides an impressive 2 terabits per second (Tb/s) of bandwidth. “This is a solution to a problem we’ve seen coming, which is the inability of external memory to keep up with the bandwidth requirements on the buffers of these ASICs,” Wheeler said. “People tried to use commodity DRAM as long as they could, but because of the pin count explosion, that reached a breaking point.” The market for communications ASICs is roughly a billion dollars, Wheeler said, noting that routers are expensive systems that can support the cost of an interposer-based (2.5D) solution to get the bandwidth required for high-speed packet buffering. For the incumbent — DDR-type DRAM running on a laminate PCB — Wheeler said “the big problem from the ASIC perspective was the pin count. You could end up with 2,000-plus-pin devices. The beauty of HBM is that it has a wide interface and stays in the package, so you don’t have to go to a serial interface.” Markets Beyond Networking? Depending how well costs can be improved, the 2.5D (interposer-based) solutions could find other applications in data processing, high-end graphics, self-driving cars, artificial intelligence, and other bandwidth-hungry solutions, said Dave McCann, vice president of packaging R&D and business technical operations at GLOBALFOUNDRIES. Moving to an interposer brings an enormous improvement in the routing density. For laminate PCB-based solutions, lines and spaces were at 12 microns, but that wiring density often was not achieved because the vertical 50-micron vias between the layers had to be avoided, or routed around, wasting a huge amount of space. With a silicon interposer, the lines and spaces are essentially the same as the back-end of a logic chip, currently about 0.8 microns, said Walter Kocon, a senior manager of technology development at GF. Using logic-like wiring for routing between the PHY and the HBM2 memory on an interposer involves using fab-level tools, including lithography. Because the interposers are much larger than conventional chips, multiple fields must be stitched together. But Kocon said today’s steppers are very good at switching between reticles, and progress is being made in creating ever-larger interposers. These fab processing tools are more expensive than conventional laminate-processing tools, but the payback is a massive number of on-chip I/Os (roughly 1,700) between the PHY and the HBM2 memory. And as McCann noted, by keeping the traces very short, power consumption is kept under control compared with the laminate-based serial interfaces used to date. No Keep Out Area “With vias enabled by wafer fab technology (<1 micron) in silicon interposers, multiple layers of 0.8-micron lines and spaces can be utilized, because there is essentially no keep out area for the vias. That compares with the conventional PCBs, where routing had to come down from the ASIC and over to the DIMM card, consuming both power and time,” McCann said. With interposer-based interconnect being orders of magnitude smaller, and devices only hundreds of microns apart, the massively parallel routing density supports multi-terabit levels of bandwidth. But there are manufacturing challenges associated with interposers. “These are big interposers and big ASICs. First, we have to create an interface between the ASIC and the interposer. Matched expansion properties of the ASIC and silicon interposer are one key to a non-stressed interface. Design and assembly processes that control warpage are critical. Then spreading the stress between the interposer and the laminate below is critical, because there is a big mismatch at that interface,” McCann said. Controlling warpage is key to getting good interconnect yields with 2.5D. With very close spacing between the interposer and the ASIC and a bump height of about 70 microns. “This means there is very little tolerance for warpage,” McCann said. Solder that is pushed together, or pulled in the opposite direction, creates connection issues. “We need manufacturing processes to keep all of these surfaces flat, and we believe, along with our OSAT partners, that we can do that,” McCann said. PHY Cooperation The PHY was another technical challenge, one that Rambus tackled along with GF. Frank Ferro, senior director of product marketing at Rambus, explained that an HBM2 PHY is a mixed signal function that must be designed very specifically to each process node. “We do a significant of amount channel modeling and then designed the PHY to meet those channel requirements. And it was a collaboration. We had many discussions over the whole process to ensure a robust design. From Day One, it worked, and that is a strong testament to the Rambus (modeling and signal integrity) tools and the engineers who have a history of designing these PHYs.” DDR DRAMs support 72 bits of bandwidth, compared with 1,024 for HBM2. With 1,024 bits, controlling the signal integrity is challenging, and Ferro tipped his cap to the GF engineers, many of whom brought experience with high-speed signaling from their days at IBM’s Microelectronics Group. Asked if he thought 2.5D solutions would spread throughout the high-performance part of the industry, Ferro said it depends on manufacturing yields, and bringing down the cost of the HBM2 DRAM. “2.5D needs to be proven out with high-volume manufacturing. It is a fairly big piece of silicon, and you have to really control warpage.” Tad Wilder, a principal member of the technical staff at GF, said the 2 terabits-per-second of bandwidth “is quite an impressive amount of bandwidth for a single core. And with the ability to place up to four HBM2 PHYs on a chip, this gives ASIC designers an unprecedented eight terabits-per-second of low power, low latency DRAM access to work with.” He added that the 14nm HBM PHY “Is the largest core we’ve produced for an ASIC, with 15,000 internal pins talking to the Memory Controller and 1,700 external pins talking to the base die of the DRAM stack across the interposer.” Each DRAM stack contains a base die, which communicates with the ASIC’s HBM2 PHY and up to eight stacked DRAM die above, through thousands of vertical Through Silicon Vias (TSVs). The total memory per HBM DRAM stack is up to 32GB. To mitigate the noise of more than 1,000 I/O possibly switching, the ASIC HBM2 PHY can take advantage of the complete independence of the eight 128 bit channels by skewing the timing of each channel with respect to another. Linley Group analyst Wheeler sees momentum building for the HBM2 standard. While Hynix was the initial backer, Wheeler said Samsung has come on strong with its own HBM2 parts. Because so much of the total solution cost is wrapped up in the cost of the HBM2 memories, competition among multiple HBM2 vendors will help drive volumes, reduce costs and improve performance. Asked if he thought 2.5D solutions would proliferate, McCann said “it is a really great technology that has come of age, with significant revenues. The question is: can we drive down the cost to get it to the next level of volume?” About Author Dave Lammers Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.
格芯展示应用于数据中心、网络和云应用的2.5D高带宽内存设计方案 August 10, 2017本方案利用2.5D封装技术,低延迟、高带宽内存PHY，使用FX-14™ ASIC设计系统搭建 加州圣克拉拉，2017年，8月9日- 格芯在今天公布，已为ASIC的14纳米高性能FinFET FX-14™集成设计平台展示了2.5D封装方案。 2.5D ASIC方案与Rambus，Inc.协作开发,包括了一个内置的插入转接板设计以克服光刻局限，也包括了每秒2T的多通道HBM2 PHY. 本方案在14纳米FinFET技术平台搭建,将集成于在7纳米 FinFET制程技术打造的下一世FX-7™ ASIC设计系统。 “由于近年来内连接和封装技术的巨大进步，制程与封装之间的分界线愈发模糊，”格芯ASIC产品发展部副总裁Kevin O’Buckley说道。“将2.5D封装应用于ASIC设计以增强性能是能力的自然进化。这让我们得以为客户提供一站式端到端的技术支持：从产品设计一直到生产和测试。” Rambus的内存PHY目标在于高端网络和数据中心应用，提供对数据要求最高的任务，满足低延迟和高带宽的系统要求。PHY技术与JEDEC JESD235 HBM2标准吻合，每个数据接口可支持高达2G的数据传输率，总带宽可达2Tbps。 “我们努力提供完善的HBM PHY技术，帮助数据中心和网络连接方案供应商达成如今最高要求的工作量，并把握住市场机会，”Rambus内存和接口分部高级副总裁、总经理Luc Seraphin说道。“我们与格芯合作，结合了我们的HBM2 PHY和格芯的2.5D封装、FX-14ASIC 设计系统，为业内告诉增长的应用提供了高度集成的设计方案。” FX-14和FX-7是完整的ASIC设计方案，利用了格芯使用FinFET制程大批量生产的经验，包含了业内应用最广泛、最具备深度的IP组合，提供了为下一代连线/5G无线网络连接、云/数据中心服务器、机器学习或深度学习、汽车和航空航天或国家防御应用的独特方案。格芯是世界上唯一两家提供最优IP和高级内存及封装方案的公司之一。 关于格芯： 格芯是提供设计开发和制造间独特组合的领先全方面服务代工厂，为全世界的先进技术公司提供服务。格芯铸造厂遍布全球三大洲，提供了改造行业的能力，为客户带来重塑市场的能力。格芯隶属Mubadala发展公司。了解更多详情，请登录网址https://www.globalfoundries.com 联系方式: Erica McGill GLOBALFOUNDRIES (518) 795-4250 [email protected]
