By: Yafeng Zhang

The booming automotive and IoT markets are driving increasing demand for microcontrollers (MCUs). Recent forecasts project that the overall MCU compound annual growth rate (CAGR) will reach 4% over the next five years, and in particular the automotive MCU CAGR could reach close to 14%.

Non-volatile memory (NVM) is a critical element of MCUs, as it is needed not only to store the code, but also to store the operating data throughout the product lifetime.

Two NVM solutions

There are two NVM solutions commonly used to build MCUs: NVM directly embedded in the system-on-chip (SoC) or a separate, external NVM chip assembled with a logic chip as a system-in-package (SiP) solution. MCUs with embedded NVM (eNVM) are fabricated in a special logic process that includes eNVM, and everything needed for MCU operation is created within that single chip. For MCUs that use a SiP solution, a NOR Flash chip and a logic chip are packaged together. Code and data are therefore stored off the logic chip on a standalone NOR Flash chip.

Top MCU providers primarily use an eNVM solution in their products, but a SiP solution may be an attractive option for smaller companies. Those companies may realize a shorter time to market, partly because using a standard, readily-available logic process may simplify and shorten the design cycle. However, a SiP solution may not meet all the requirements of many IoT and automotive applications. Using eNVM will often be the superior solution given the the cost, power, speed, security, stability, and reliability requirements of high growth MCU applications.

Choosing the best solution

To choose the best solution for an application, consider the following comparison of these two solutions based on key end market requirements of power consumption, power-up time, speed, security, reliability and cost:

• Power Consumption: eNVM offers more than 30% lower active power consumption than SiP because SiP flash requires constant IO toggle. Therefore, GF recommends eNVM for battery powered IoT applications that require low power. GF and eVaderis are co-developing a low power MCU using 22FDX and eMRAM
• Power-up Time: eNVM offers a 20x faster time to power up and access first data than SiP (5µs vs. 100µs) because eNVM is XIP, whereas with SiP flash, the system needs to copy the data to on-chip SRAM. Therefore, for normally-off applications that require very fast power-up and read times, GF recommends embedded eNVM.
• Speed: eNVM offers a 2x faster read speed than SiP (400MB/sec vs. 200MB/sec), since the eNVM macros have x32 to x128 bit IO bus width, whereas the SiP uses x4 or x8 bit Therefore, GF recommends eNVM for high speed/high bandwidth applications.
• Security: eNVM offers higher security than SiP because the eNVM macro can be customized and the SoC can use IP such as PUF to enhance security. In contrast, SiP flash is a standard offering in the market, and extra security cannot be added. So, GF recommends eNVM for high security applications.
• Reliability: eNVM offers higher reliability because it is qualified as a single SoC by the required reliability level, whereas SiP flash can only achieve high reliability by adding strict test screening on known good die (KGD) and the package. CMOS Embedded STT-MRAM arrays in 2x nm Modes for GP-MCU applications
• Cost: To compare the cost of the two solutions, several factors must be taken into account:
  • NVM memory density and full chip size, which determines the Gross-Die-Per-Wafer with or without eNVM
  • Wafer price, with or without eNVM
  • Extra on-chip SRAM density for SiP solution, which is used to download the code from external Flash during power up
  • Flash KGD price for SiP solution
  • Wafer testing cost, with or without eNVM
  • Additional factors like wafer yield, with or without eNVM, SiP solution FT yield loss, management cost

Comparing cost

The following cost comparison includes six typical NVM memory densities (2Mb, 4Mb, 8Mb, 16Mb, 32Mb, 128Mb) implemented both on GF’s 40nm LPx platform with eFlash, and also on the 22FDX® (22nm FD-SOI) platform with eMRAM.

Because every company has a different power up methodology for SiP solutions, various on-chip SRAM densities are used to “shadow” the external Flash. The following results assume the ideal case for SiP, where a SiP solution and eNVM solution utilize an identical SRAM size. Note that most common SiP solutions increase the SRAM size for code shadowing from the external Flash.

Source: GLOBALFOUNDRIES, 2018

The graph above shows that the 40nm platform with eNVM (eFlash) is lower cost when the NVM density is less than 16Mb, while the SiP solution is lower cost when the NVM density is equal to, or higher than 16Mb.

For a design utilizing 22nm FDX platform, the eNVM solution (eMRAM) is lower cost when the NVM density is less than 32Mb, while the SiP solution is lower cost when the NVM density is equal to or higher than 32Mb.

Comparing the two platforms, the 22FDX eNVM solution (eMRAM) has lower cost at all the NVM densities versus the 40nm SiP solution. In addition, for the 22nm platform the additional cost for eMRAM at higher densities (32Mb+) is 4% or less, while also outperforming a SiP solution in power, speed, security, and reliability.

For even larger SRAM densities, the advantages of an eNVM solution are even greater.

So, which solution is best for my MCU?

In summary, both eNVM and SiP solutions are viable methods to combine logic and NVM. However, eNVM is often a better choice for MCUs based on the superior power, speed, security and reliability. With respect to cost, eNVM is often a lower cost than SiP, especially below 32Mb NVM densities. As MCU makers consider all the trade-offs for their products, GF stands ready to assist clients in selecting the appropriate solution to win in their market.

In a recent Tech Talk video GF talks about the pros and cons of embedded non-volatile memory versus system in package.

GF offers a wide range of eNVM and SiP solutions using leading-edge and mainstream technology platforms from 130nm to 22nm to meet the diverse needs of emerging markets. The low power consumption of the cell core eMRAM series is ideal for the MCU and IoT markets, with ultra-fast access speeds and high storage capacity making it the perfect companion for the computing and storage markets. eFlash solutions (plus RF and analog modules and a variety of IP) are optimized for specific applications such as wearables, IoT, automotive, industrial and consumer electronics.  GF SiP solutions offer fast time-to-market with proven technology.

Please contact GF for a precise comparison of SiP vs. eNVM for your specific MCU architecture.

About Author

Yafeng Zhang

Yafeng has about 15 years of experience in the semiconductor industry, with expertise in design, application and technical marketing of NOR flash. Yafeng drives the technical marketing of the eFlash product offerings from 130nm to 40nm, with particular focus on the automotive and industrial MCU customers.

Before joining GF, Yafeng had the senior engineering roles, most recently at Micron Semiconductor where he focused on 45nm NOR flash design and products application. Prior to that, Yafeng held various positions at Synopsys and SMIC.

Yafeng holds a Master of Engineering degree in Micro Electronics, and a Bachelor’s degree in Materials Science from Fudan University, Shanghai, China.

By: Dave Lammers

“There are far fewer bigots out there than there were two years ago.” Dan Hutcheson, CEO of VLSI Research

Two years ago, when Dan Hutcheson, CEO of market research firm VLSI Research Inc. (Santa Clara, Calif.), set out to interview influential IC and intellectual property managers about fully depleted silicon on insulator (FD-SOI), he found two top-of-mind concerns: the availability of external IP which design teams could combine with internal intellectual property, and the then-lack of a process technology roadmap.

Hutcheson redid the VLSI Research survey this year and found a different landscape: the 2018 survey respondents were much less concerned with the roadmap issue now that GLOBALFOUNDRIES has committed to a 12nm node for its FDX technology, and “IP is much less of an issue,” Hutcheson said during a presentation of the 2018 survey results at the 2018 SOI Silicon Valley Symposium in late April.

Hutcheson asked 24 people—decision-makers at companies accounting for more than half of the IC and intellectual property markets—about  the transistor reasons to design with FD-SOI. Nearly 40 percent cited “better gain for analog” as the top reason, with a similar number citing lower leakage and better parasitics. Lower noise, better transistor matching, thermal properties, reliability concerns, and better radiation protection followed in importance.

The 2018 survey participants are now aware that RF and mixed-signal technologies are more readily implemented in FD-SOI, including a widely held view that FD-SOI is a better solution for 5G and millimeter-wave RF SoCs.

Times Have Changed

When the 2016 survey was conducted, finFET-based processes were just becoming available. At that time people were thinking in either-or mode: either finFETs or FD-SOI, one or the other. Now that finFETs have become widely available, more nuanced thinking is taking hold. “Now, most people have said finFETs and FD-SOI are complementary technologies, and which one you use depends on application needs,” Hutcheson said.

FinFET-based technologies offer higher performance, integration, and density. However, the design and mask costs are higher than FD-SOI, even though finFET costs have come down over the last two years due to depreciation of tool sets.

Many of the survey respondents said the primary advantages of FD-SOI centered on RF, or “high-mix SoCs” with analog, digital, and RF on the same die. In product markets where RF and sensor integration are valuable, FD-SOI is seen as the way to go “much more than before,” he said.

The respondents told Hutcheson that the fully depleted planar transistors on SOI offer “better gain for analog, better matching, and they are much easier to match. The automotive guys see a better thermal range, and more stable operation” in automotive environments. Also, analog designs benefit from the better gain possible with the FD-SOI depletion-mode transistors, compared with the enhancement-mode transistors of finFETs.

“FD-SOI is uniquely positioned for 5G because of the better parasitics. Some people are trying to use fins for 5G, but fin parasitics are a deciding factor. To paraphrase the respondents, ‘You can always find a way to engineer around anything. But the question is: How much do you want to pay to engineer around that?’” he said.

The 2018 survey asked for the top reasons to favor finFETs. The largest reasons were the performance and density advantages held by leading-edge finFETs. Nearly 30 percent said “FD is not cost-effective on a structural basis in these domains.”  About 15 percent of the respondents said they believe millimeter-wave ICs are “possible to do with bulk.” Others cited a wide variety of reasons for preferring finFETs, including challenges in designing with back-biasing, the finFET ecosystem “has no peers,” a lack of FD-SOI IP, and “management says no.”

“I asked about body-biasing and found people who said it was oversold,” Hutcheson said. One person said “if I go to my boss and say, we ought to do this because we want to do body-biasing, he is likely to say it is too complex and risky, so just do bulk. It’s better to first sell them on FD’s unique transistor features to management first and then add body-biasing as a bonus later.”

The respondents said FD-SOI had business-reason attractiveness, with about 30 percent citing lower design costs as the top business reason to design with FD-SOI. Lower manufacturing costs, fewer masks, and faster cycle-times/ time-to-market followed.

Hutcheson noted that the Internet of Things label encompasses several large market segments. For edge IoT markets where power consumption is important—which he referred to as “clever power with on/off mission profiles” —FD-SOI “has a huge advantage.” And, he said the survey indicated FD-SOI has advantages for markets where the product life is short, and for companies that have ”low budgets for chip design.”

The main takeaway from the 2018 survey is that managers and engineers are more willing to consider FD-SOI as a complement to finFETs, or in some cases as the only process roadmap that fits their company’s product requirements. Fully 75 percent of the survey respondents said they would consider running two roadmaps, one for finFETs and another for FD-SOI.

“Two years ago, people had a dramatic take on the question: is it finFETs? Or is it FD-SOI? At that time it was an OR-gate kind of situation, but now it is more like an AND gate. People are willing to use both. There are far fewer bigots out there than there were two years ago,” he said.

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.