New ARM POP technology provides core-hardening acceleration for Cortex-A12 and Cortex-A7 processors

Milpitas, Calif., and Cambridge, UK, June 3, 2013 – In conjunction with the launch of the ARM® Cortex®-A12 processor, ARM and GlobalFoundries today announced new power, performance and cost-optimized POP™ technology offerings for the ARM Cortex-A12 and Cortex-A7 processors for GF 28nm-SLP High-K Metal Gate (HKMG) process technology. The Cortex-A12 processor was introduced by ARM today as part of a suite of IP targeting the rapidly growing market for mid-range mobile devices.

The companies will combine ARM’s next-generation mobile processor and POP IP with GF 28nm-SLP HKMG process solution, enabling a new level of system performance and power efficiency with the optimum economics necessary to serve the mid-range mobile device market. The new initiative builds on the existing robust ARM Artisan® physical IP platform and POP IP for the Cortex-A9 processor already available on GF 28nm-SLP, signifying another milestone in the multi-year collaboration between ARM and GF.

Central to this increase in functionality for mid-range mobile devices is the new ARM Cortex-A12 processor. The Cortex-A12 processor provides a 40 percent performance uplift and direct upgrade path from the incredibly successful Cortex-A9 processor while matching the energy efficiency of its predecessor. The Cortex-A12 processor provides best-in-class efficiency as a standalone solution, but additionally supports the innovative big. LITTLE™ processing technology with the Cortex-A7 processor, bringing this energy-efficient technology to the mid-range. GF 28nm-SLP process technology and associated ARM POP IP for the Cortex-A12 processor enables up to 70 percent higher performance (measured single-thread performance) and up to 2x better power efficiency in comparison to a Cortex-A9 processor using 40nm process technology. Designers can achieve even higher performance by trading off for lower power efficiency, depending on their application needs.

The newest POP technology enables customers to accelerate core-hardening of Cortex-A12 and Cortex-A7 processors on GF 28nm-SLP HKMG process. POP IP for Cortex processors has successfully enabled ARM-based SoCs with more than 30 different licenses since being introduced over three years ago. POP IP is composed of three elements necessary to achieve an optimized ARM processor implementation: core-specific tuned Artisan physical IP logic libraries and memory instances, comprehensive benchmarking reports, and implementation knowledge that detail the methodology used to achieve the result, to enable the end customer to achieve the same implementation quickly and at low risk.

“With 580 million mid-range smartphones and tablets forecast to be sold in 2015, consumers are increasingly looking for the right combination of performance, low power and cost effectiveness,” said Dr. Dipesh Patel, executive vice president and general manager, Physical IP Division at ARM. “With the Cortex-A12 processor and suite of IP announced today, ARM is delivering an optimized system solution leveraging the most innovative technologies available for this market. The POP IP solution on GF 28nm-SLP helps designers balance the performance, power and cost tradeoffs to achieve their targets for this growing market.”

GF 28nm-SLP technology is ideally suited for the next generation of smart mobile devices, enabling designs with faster processing speeds, smaller feature sizes, lower standby power and longer battery life. The technology is based on GF’s “Gate First” approach to High-K Metal Gate (HKMG), which has been in volume production for more than two years. The technology offers a combination of performance, power efficiency and cost that is ideally suited for the mid-range mobile market.

“GF is committed to a deep relationship with ARM to enable best-in-class solutions for our mutual customers. Our collaboration on the ARM Cortex-A12 processor implementation is a direct result of this focus and collaboration,” said Mike Noonen, executive vice president of Marketing, Sales, Design and Quality at GF.

GF’s next-generation 14nm-XM FinFET technology is expected to bring another dimension of enhanced power, performance and area for ARM mobile processors. A Cortex-A9 processor implemented on 14nm-XM technology, using 9-track libraries, is projected to enable a greater than 60 percent increase in frequency at constant power, or a decrease of more than 60 percent in power consumption at constant performance, when compared to implementation on 28nm-SLP technology using 12-track libraries. Similar results are expected for Cortex-A12 processor implementations. Click here for more details on GF’s 14nm-XM FinFet technology.

For further discussions about GF process technologies or ARM IP offerings please visit the companies’ respective exhibits at the Design Automation Conference (DAC), June 3-5, 2013 in Austin, Texas. ARM is located in booth 931, and GF can be found at booth 1314.

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About ARM

ARM designs the technology that is at the heart of advanced digital products, from wireless, networking and consumer entertainment solutions to imaging, automotive, security and storage devices. ARM’s comprehensive product offering includes RISC microprocessors, graphics processors, video engines, enabling software, cell libraries, embedded memories, high-speed connectivity products, peripherals and development tools. Combined with comprehensive design services, training, support and maintenance, and the company’s broad Partner community, they provide a total system solution that offers a fast, reliable path to market for leading electronics companies. Find out more about ARM by following these links:

The secrets of success from the Connected Community surrounding ARM

ARM website: https://www.arm.com
ARM Connected Community®: https://www.arm.com/community
ARM Blogs: https://blogs.arm.com
ARMFlix on YouTube: https://www.youtube.com/armflix

ARM on Twitter:

https://twitter.com/ARMPROffice
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https://twitter.com/ARMMobile
https://twitter.com/ARMCommunity
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https://twitter.com/ARMSoC
https://twitter.com/ARMTools
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ABOUT GF

GF is the world’s first full-service semiconductor foundry with a truly global footprint. Launched in March 2009, the company has quickly achieved scale as the second largest foundry in the world, providing a unique combination of advanced technology and manufacturing to more than 160 customers. With operations in Singapore, Germany and the United States, GF is the only foundry that offers the flexibility and security of manufacturing centers spanning three continents. The company’s three 300mm fabs and five 200mm fabs provide the full range of process technologies from mid-range to the leading edge. This global manufacturing footprint is supported by major facilities for research, development and design enablement located near hubs of semiconductor activity in the United States, Europe and Asia. GF is owned by the Advanced Technology Investment Company (ATIC). For more information, visit https://www.gf.com.

Jointly developed with leading EDA providers, flows address AMS challenges from specification to verification; complete flows for digital design for double patterning

Milpitas, Calif. — May 30, 2013 — At next week’s 50th Design Automation Conference (DAC) in Austin, Texas, GLOBALFOUNDRIES will unveil a comprehensive set of certified design flows to support its most advanced manufacturing processes. The flows, jointly developed with the leading EDA providers, offer robust support for implementing designs in the company’s 20nm low power process and its leading-edge 14nm-XM FinFET process. Working closely with Cadence Design Systems, Mentor Graphics and Synopsys, GF has developed the flows to address the most pressing design challenges, including support for analog/mixed signal (AMS) design, and advanced digital designs, both with demonstration of the impact of double patterning on the flow.

The GF design flows work with its process design kits (PDKs) to provide real examples that demonstrate the entire flow. The user can download the design database, the PDK, detailed documentation and multi-vendor scripts to learn how to set up and use the GF design flow. The flows use open source examples and provide the customer with working, executable and customizable flows.

“As the developer of the industry’s first modular 14nm FinFET technology and one of the leaders at 20nm, we understand that enabling designs at these advanced process nodes requires innovative methodologies to address unprecedented challenges,” said Andy Brotman, vice president of design infrastructure at GF. “By working with a new level of collaboration with EDA partners, we can provide enhanced insight into our manufacturing processes in order to fully leverage the capabilities of 20nm and 14nm manufacturing. This provides our mutual customers with the most efficient, productive and risk-reduced approach to achieving working silicon.”

Production Ready AMS flow from specification to verification

To address the unique requirements of analog/mixed signal (AMS) design at advanced processes, GF has enhanced its design flows to provide production quality scripts and packaged methodologies. The new reference flow establishes a working flow from specification to physical verification that has been taped out to be verified on working silicon.

The AMS reference flow provides comprehensive double pattern design guidelines. It gives overview of decomposition flow for both block level and chip level. The flow also addresses decomposition for different design styles. Recommendations for color balancing, hierarchical decomposition, ECO changes are discussed. The flows also present decomposition impact on DRC run time and resulted database size.

Notably, the reference flow includes support for efficiency and productivity improvements in the Cadence Virtuoso® environment specifically for designing in a double patterned process. The flow includes support for Virtuoso Advanced Node 12.1 and provides efficient access to the tool’s productivity benefits for physical design with real-time, color-aware layout. Circuit designers can assign “same net” constraints in the schematic, and the layout designers can meet these requirements as they create the physical view. Additionally, layout designers can take advantage of Virtuoso tool support for local interconnect, and advanced layout dependent effect management.

The flow also features interoperability with Mentor’s Calibre® nmDRC™, nmLVS™, and extraction products which address multipatterning requirements for both double and triple patterning. In addition special settings for analog design; auto-stitching and when to use it; and fill and color balancing are described in detail.

The AMS flow provides detailed information on parasitic extraction and layout dependent effects, both of which introduce new challenges at 20nm and 14nm. For parasitic extraction, the flows are described in detail and customizable scripts and examples demonstrate OA and DSPF back annotation. In addition the flows illustrate methodologies to predict layout-dependent effects during schematic design and methods to include full models in post layout extraction. PEX flows for Synopsys StarRC™ extraction, Cadence QRC and Mentor CalibrexRC™ are supported.

These flows serve as references to validate the correctness of the accompanying PDK as well as the vendor tools setup.

Sign-off ready RTL2GDSII flows that address double patterning

GF is also making available new flows that support a complete RTL-to-GDSII design methodology for targeting its 20nm and 14nm manufacturing processes. The company worked with EDA vendors to certify the flows in their respective environments and provide a platform for optimized, technology-aware methodologies that take full advantage of the performance, power and area benefits of the processes.

The result is a set of fully executable flows containing all the scripts and template files required to develop an efficient methodology. The flows serve as a reference to validate the correctness of the accompanying PDK as well as the vendor tool setup. In addition the flows offer access to other critical and useful information, such as methodology tutorial papers; guidelines and methodologies for decomposition of double patterned layouts; PEX/STA methodology recommendations and scripts; and design guidelines and margin recommendations.

A critical aspect of manufacturing at this level is the use of double patterning, an increasingly necessary technique in the lithographic process at advanced nodes. Double patterning extends the ability to use current optical lithography systems and the GF flows provide comprehensive double pattern design guidelines. They address design for double patterning and the added flow steps for different design styles and scenarios.

This includes support for odd cycle checking, a new type of DRC rule that must be met to allow for legal decomposition of the metals into two colors. This check is detailed in the flow and guidelines are provided to make sure it is met.

Synopsys and GF worked together to minimize the impact of changes associated with the 3-D nature of FinFET devices as compared to planar transistors. The two companies focused on making FinFET adoption transparent to the design team. The collaboration on Synopsys’ RTL to GDSII flow includes 3-D parasitic extraction with the Synopsys StarRC™ tool, SPICE modeling with the Synopsys HSPICE® product, routing rules development with the Synopsys IC Compiler™ tool and static timing analysis with the Synopsys PrimeTime® tool.

Cadence contributed a complete RTL-GDSII flow, including physical synthesis, and planning and routing developed with the Encounter® Digital Implementation (EDI) System foundation flow. The seamless implementation flow, using Cadence Encounter RTL Compiler and EDI System, supports double patterning and advanced 20- and 14-nm routing rules.

Mentor’s Olympus-SoC™ place and route system is supported in the flow, providing support for new DRC, double patterning, and DFM rules. The Olympus-SoC router has its own native coloring engine along with verification and conflict resolution engines that detect and automatically fix double patterning violations. Expanded features include DP-aware pattern matching, coloring aware pin access, pre-coloring of critical nets, and DP aware placement. The Calibre® InRoute™ product allows Olympus-SoC customers to natively invoke Calibre signoff engines during design for efficient and faster manufacturing closure.

Double patterning also impacts LVS and other DRC issues, and the flows provide methodology details to address these areas, including hierarchical decomposition to reduce data base explosion. Parasitic extraction methodologies and scripts are provided as well, offering ways to address double patterning-induced variations via DPT corners or with maskshift PEX features.

About GF

GF is the world’s first full-service semiconductor foundry with a truly global footprint. Launched in March 2009, the company has quickly achieved scale as the second largest foundry in the world, providing a unique combination of advanced technology and manufacturing to more than 160 customers. With operations in Singapore, Germany and the United States, GF is the only foundry that offers the flexibility and security of manufacturing centers spanning three continents. The company’s three 300mm fabs and five 200mm fabs provide the full range of process technologies from mainstream to the leading edge. This global manufacturing footprint is supported by major facilities for research, development and design enablement located near hubs of semiconductor activity in the United States, Europe and Asia. GF is owned by the Advanced Technology Investment Company (ATIC). For more information, visit https://www.globalfoundries.com.

Collaboration with leading EDA vendors supports complete range of steps required to create and verify advanced stacking implementations using TSV and interposer approaches

Milpitas, Calif. — May 30, 2013 — At next week’s 50th Design Automation Conference (DAC) in Austin, Texas,GLOBALFOUNDRIES will unveil a comprehensive set of certified design flows to support 2.5D IC product development with its most advanced manufacturing processes. The sign-off ready flows, jointly developed with the leading EDA providers, offer robust support for implementing designs using sophisticated multi-die packaging techniques, leveraging through-silicon vias (TSVs) in 2.5D silicon interposers and new bonding approaches.

Multi-vendor support is available, with full implementation flows from Synopsys and Cadence Design Systems. Physical verification with Mentor Graphics’ suite of tools is included in the flow.

The GF 2.5D technology addresses the challenges of multi-die integration with solutions for front-end steps such as via-middle TSV creation, and flexibility for the backend steps, like bonding/debonding, grinding, assembly, and metrology.

“Our 2.5D technology provides designers with a path to enable heterogeneous logic and logic/memory integration, offering increased performance and reduced power consumption, without the need for additional packages,” said Andy Brotman, vice president of design infrastructure at GF. “These benefits can now be realized very efficiently with certified design flows that provide support for the additional steps and design rules involved in the design process. By working closely with our EDA partners, we can greatly reduce the development time and time-to-production using the most advanced multi-die approaches.”

The flows allow designer to quickly and reliably address the additional requirements of 2.5D design, including top-level interposer design creation and floor planning, as well as the increased complexity of using TSVs, front-side and back-side bumps, and redistribution layer (RDL) routing. The flows support the need for additional verification steps brought on by 2.5D design rules.

The design flows work with GF’s process design kits (PDKs) to provide real examples that demonstrate the entire flow. The user can download the design database, the PDK, detailed documentation and multi-vendor scripts to learn how to set up and use the GF design flow. The flows use open source examples and provide the customer with working, executable and customizable flows.

The flows come with a CPU core and memory IP and all the scripts and settings to execute a Synopsys Galaxy™ Implementation Platform-based flow or Cadence Encounter®-based implementation flows with the GF PDK. Similarly, the Mentor Calibre® 3DSTACK tool is exercised in the flow to verify DRC, LVS and extraction within and between the various die stacks leveraging the same golden design kits as used inside of GF.

Comprehensive design support

The flows provide support for a complete 2.5D design flow. This includes RDL routing between chips on interposer and RDL routing to IO pads. The flows demonstrate all the steps involved in chip pad setup, C4 and microbump placement, and TSV alignment. Designers can use the flows to be guided through processes such as creating top die (logic and memory) with microbumps, followed by interposer creation – including floor planning, microbump, TSV and C4 Bump placement, power mesh generation and signal routing.

The flow incorporates the Cadence 3D-IC solution, which supports all three driving design methodologies: package driven, SoC driven, and custom driven. The solution has been proven on a number of designs ranging from 2.5D to full 3D. All of the requisite technology features are supported and accessible across environments to help unify the design, analysis and signoff tasks on the multiple die and substrate. The Cadence 3D-IC solution includes the Encounter Digital Implementation System with a 3D option.

The Synopsys Galaxy Implementation Platform has been enhanced specifically to address 2.5D design. Designers can implement the Synopsys IC Compiler™ tool for placement, assignment and routing of microbump, TSV, probe-pad and C4; microbump alignment checks; RDL and signal routing, and power mesh creation on silicon interposer interconnection layers. Advanced verification and analysis support is also available for layout vs. schematic (LVS) connectivity and design rule checking (DRC) between stacked die; parasitic extraction for TSV, microbump, RDL; signal routing metal for stacked die and silicon interposer design interconnection; and timing analysis of multi-die systems.

The flows allow for interposer and top-die physical/logical interface and alignment checks at various stages in the design phase. Mentor’s Calibre can be used to verify physical offset, rotation, and scaling at die interfaces. The Calibre 3DSTACK product also enables connectivity tracing and extraction of interface parasitic elements needed for multi-die performance simulation.

• Galaxy Implementation Platform

About GF

GF is the world’s first full-service semiconductor foundry with a truly global footprint. Launched in March 2009, the company has quickly achieved scale as the second largest foundry in the world, providing a unique combination of advanced technology and manufacturing to more than 160 customers. With operations in Singapore, Germany and the United States, GF is the only foundry that offers the flexibility and security of manufacturing centers spanning three continents. The company’s three 300mm fabs and five 200mm fabs provide the full range of process technologies from mainstream to the leading edge. This global manufacturing footprint is supported by major facilities for research, development and design enablement located near hubs of semiconductor activity in the United States, Europe and Asia. GF is owned by the Advanced Technology Investment Company (ATIC). For more information, visit https://www.globalfoundries.com.

STT-MRAM offers enhanced performance and scalability for embedded and standalone applications

Leuven (Belgium) — May 21, 2013 — Imec and GLOBALFOUNDRIES announced today that they have expanded joint development efforts to advance STT-MRAM (spin-transfer torque magnetoresistive random access memory) technology.

The first IC manufacturer to join imec’s R&D program on emerging memory technologies, GF completes the value chain of imec’s research platform, which fuels industry collaboration from technology up to the system level. GF is joining a team with a leading fabless company (https://www2.imec.be/be_en/press/imec-news/qualcomm2013.html) and several worldwide equipment suppliers providing the complete infrastructure necessary for R&D on STT-MRAM.

STT-MRAM technology is a promising high-density alternative to existing memory technologies, like SRAM and DRAM. Together, imec and the program members aim to explore the potential of STT-MRAM, including performance below 1nanosecond (ns) and scalability beyond 10 nanometers (nm) for embedded and standalone applications.

“We are elated to intensify our collaboration with GF and the other program members on advanced memory technologies—a true testament to the value we offer our industrial partners,” stated Luc Van den hove, president and CEO at imec. “Our unique research environment harnesses the collective expertise and knowledge of the entire value chain, bringing together foundries, IDMs, fabless and fablite companies, packaging and assembly companies, and equipment and material suppliers to drive innovation and the development of new, competitive products.”

“Innovation in next-generation memory is required to give chip designers new options to continue to deliver leading-edge products with higher performance, lower power-consumption, and better bandwidth,” said GF chief technology officer Gregg Bartlett. “This new partnership with imec will enable close collaboration with customers, partners, and the supplier community to help reduce the risk in bringing this new memory technology to market.”

About imec

Imec performs world-leading research in nanoelectronics. Imec leverages its scientific knowledge with the innovative power of its global partnerships in ICT, healthcare and energy. Imec delivers industry-relevant technology solutions. In a unique high-tech environment, its international top talent is committed to providing the building blocks for a better life in a sustainable society. Imec is headquartered in Leuven, Belgium, and has offices in Belgium, the Netherlands, Taiwan, US, China, India and Japan. Its staff of close to 2,000 people includes more than 600 industrial residents and guest researchers. In 2011, imec’s revenue (P&L) was about 300 million euro. Further information on imec can be found at www.imec.be.

Imec is a registered trademark for the activities of IMEC International (a legal entity set up under Belgian law as a “stichting van openbaar nut”), imec Belgium (IMEC vzw supported by the Flemish Government), imec the Netherlands (Stichting IMEC Nederland, part of Holst Centre which is supported by the Dutch Government), imec Taiwan (IMEC Taiwan Co.) and imec China (IMEC Microelectronics (Shangai) Co. Ltd.) and imec India (Imec India Private Limited).

About GF

GF is the world’s first full-service semiconductor foundry with a truly global footprint. Launched in March 2009, the company has quickly achieved scale as the second largest foundry in the world, providing a unique combination of advanced technology and manufacturing to more than 160 customers. With operations in Singapore, Germany and the United States, GF is the only foundry that offers the flexibility and security of manufacturing centers spanning three continents. The company’s three 300mm fabs and five 200mm fabs provide the full range of process technologies from mainstream to the leading edge. This global manufacturing footprint is supported by major facilities for research, development and design enablement located near hubs of semiconductor activity in the United States, Europe and Asia. GF is owned by the Advanced Technology Investment Company (ATIC). For more information, visit https://www.globalfoundries.com.

Contact:

Hanne Degans, External Communications Officer, T: +32 16 28 17 69, Mobile: +32 486 065 175 begin_of_the_skype_highlighting +32 486 065 175 FREE end_of_the_skype_highlighting, [email protected]

Singapore, May 6, 2013 — KC Ang, Senior Vice President and General Manager of GLOBALFOUNDRIES Singapore, has been appointed to serve SEMI Singapore Regional Advisory Board (RAB) as their new chairman effective immediately.

A semiconductor industry veteran, Ang has held various senior leadership roles in GF, including recent positions at the company’s global manufacturing sites outside Singapore – Fab 1 in Germany and Fab 8 in the United States – to help accelerate the transformation of those sites into pure-play world class foundry operations.

Having worked in the industry for more than 25 years, Ang brings a wealth of foundry experience and expertise to SEMI Singapore RAB, an advisory group of industry executives chartered to drive SEMI’s mission in promoting growth and increasing visibility of the semiconductor industry in Southeast Asia.

“I am honored to be selected as the chairman of the SEMI Singapore RAB,” said Ang. “The semiconductor industry in this region has developed into a vibrant and robust ecosystem today, and Singapore with her rich semiconductor heritage plays a leading role in the contribution. I look forward to sharing our foundry’s global knowledge and working with my industry peers to further promote and enhance the industry footprint within Singapore and regionally.”

“On behalf of SEMI Singapore and its members, I am pleased to welcome KC Ang to the Board,” said Terry Tsao, president of SEMI Southeast Asia. “Alongside with other distinguished industry leaders who joined our Board as executive directors, I believe under the chairmanship of KC, the team will continue to spearhead activities that can help drive growth in the semiconductor industry for this region.”

ABOUT GF

GF is the world’s first full-service semiconductor foundry with a truly global footprint. Launched in March 2009, the company has quickly achieved scale as the second largest foundry in the world, providing a unique combination of advanced technology and manufacturing to more than 150 customers. With operations in Singapore, Germany and the United States, GF is the only foundry that offers the flexibility and security of manufacturing centers spanning three continents. The company’s three 300mm fabs and five 200mm fabs provide the full range of process technologies from mainstream to the leading edge. This global manufacturing footprint is supported by major facilities for research, development and design enablement located near hubs of semiconductor activity in the United States, Europe and Asia. GF is owned by the Advanced Technology Investment Company (ATIC). For more information, visit https://www.globalfoundries.com.

Media Contact:

Gina Wong
(65) 6670-8108
[email protected]

Lim Wei Lee
(65) 6670-1821
[email protected]

Neubiberg / Dresden, Germany and Singapore — April 29, 2013 — Infineon Technologies (FSE: IFX / OTCQX: IFNNY) and GlobalFoundries Inc. today announced a joint technology development and production agreement for 40 nanometer (nm) embedded flash (eFlash) process technology. The cooperation will focus on technology development based on Infineon’s eFlash cell design and manufacturing of automotive and security microcontrollers (MCUs) with 40nm process structures. Production of the next generation 40nm eFlash MCUs will take place at different GF sites, initially in Singapore with subsequent transfer to its site in Dresden, Germany.

“Next-generation embedded Flash microcontrollers with 40nm process structures will further enhance our competitive strength in the automotive as well as chip card and security markets,” says Arunjai Mittal, Member of the Management Board of Infineon Technologies. “We trust in GF with their excellent manufacturing background and sites on different continents to fulfill Infineon’s stringent quality, infrastructure security and business continuity requirements.”

“Infineon’s decision to choose GF as the foundry partner for the 40nm embedded Flash technology node recognizes our unique ability to offer one-foundry-solutions supported by multiple fabs in different geographies,” says Ajit Manocha, CEO GF. “We are committed to providing leading-edge technology and manufacturing capabilities required to support Infineon’s business. We are looking forward to a long-term collaboration with Infineon and to contribute to its success in a very dynamic industry.”

This agreement with GF is consistent with Infineon’s strategy to engage in technology co-development for CMOS-based technologies in 65nm and below. Process and product qualification for security microcontrollers is planned for the second half of 2015. Automotive microcontroller production start is scheduled for the first half of 2017.

Infineon and GF have a longstanding relationship in development and manufacturing, including joint development and manufacturing of CMOS-based low-power mobile phone products.

About GF

GF is the world’s first full-service semiconductor foundry with a truly global footprint. Launched in March 2009, the company has quickly achieved scale as the second largest foundry in the world, providing a unique combination of advanced technology and manufacturing to more than 160 customers. With operations in Singapore, Germany and the United States, GF is the only foundry that offers the flexibility and security of manufacturing centers spanning three continents. The company’s three 300 mm fabs and five 200 mm fabs provide the full range of process technologies from mainstream to the leading edge. This global manufacturing footprint is supported by major facilities for research, development and design enablement located near hubs of semiconductor activity in the United States, Europe and Asia. GF is owned by the Advanced Technology Investment Company (ATIC). For more information, visit https://www.gf.com.

About Infineon

Infineon Technologies AG, Neubiberg, Germany, offers semiconductor and system solutions addressing three central challenges to modern society: energy efficiency, mobility, and security. In the 2012 fiscal year (ending September 30), the Company reported sales of Euro 3.9 billion with close to 26,700 employees worldwide. Infineon is listed on the Frankfurt Stock Exchange (ticker symbol: IFX) and in the USA on the over-the-counter market OTCQX International Premier (ticker symbol: IFNNY).

This news release is available online at www.infineon.com/press and at www.gf.com/news-events/globalfoundries-press-releases.

Press Contacts at GF:

Gina Wong
Public Relations, Singapore
Phone: +65 6670-1808 begin_of_the_skype_highlighting +65 6670-1808 FREE end_of_the_skype_highlighting
Email: [email protected]

Karin Raths
EMEA Communications, Dresden, Germany
Phone: +49 351 277-1013 begin_of_the_skype_highlighting +49 351 277-1013 FREE end_of_the_skype_highlighting
Email: [email protected]

Press Contacts at Infineon Technologies:

Karin Braeckle
Media Relations, Neubiberg, Germany
Phone: +49 89-23424 begin_of_the_skype_highlighting +49 89-23424 FREE end_of_the_skype_highlighting
Email: [email protected]

Chi Kang David Ong
Media Relations, Singapore
Phone: +65 6876-3070 begin_of_the_skype_highlighting +65 6876-3070 FREE end_of_the_skype_highlighting
Email: [email protected]

Milpitas, Calif., April 22, 2013 — GLOBALFOUNDRIES today announced that the appointment of a new country manager for its sales office in Japan.

Shigeru (Gerry) Shimauchi joins the world’s second largest foundry from InvenSense, a US-based fabless company that specializes in motion-sensing devices for consumer electronics products. At InvenSense, he was the country manager responsible for driving sales revenue.

Reporting to Craig Luhrmann, Vice President of Japan and Korea Sales at GF, Shimauchi is responsible for the company’s sales and business development in Japan.

“We are pleased to have Gerry on board with us. His broad experience and depth of relationships within the Japanese semiconductor market will strengthen our accelerating foundry engagements with the Japanese integrated device manufacturers,” said Luhrmann. “Gerry will act as our local contact for sales activities and drive our goal in becoming the foundry partner of choice.”

Shimauchi brings 30 years of industry experience to the role in GF, including his last 10 years in leading sales for the Japan market

Gerry brings 30 years of industry experience to the role, including the last 10 years leading Japan sales, most recently for InvenSense, and previously with Cirrus Logic, Impinj, MoSys International and Nippon Sipex. He also held operational leadership roles with TSMC Japan, Burr-Brown, and Fujitsu where he started his career as a sales engineer. Shimauchi graduated from Yokohama National University in 1982.

ABOUT GF

GF is the world’s first full-service semiconductor foundry with a truly global footprint. Launched in March 2009, the company has quickly achieved scale as the second largest foundry in the world, providing a unique combination of advanced technology and manufacturing to more than 150 customers. With operations in Singapore, Germany and the United States, GF is the only foundry that offers the flexibility and security of manufacturing centers spanning three continents. The company’s three 300mm fabs and five 200mm fabs provide the full range of process technologies from mainstream to the leading edge. This global manufacturing footprint is supported by major facilities for research, development and design enablement located near hubs of semiconductor activity in the United States, Europe and Asia. GF is owned by the Advanced Technology Investment Company (ATIC). For more information, visit https://www.globalfoundries.com.

55nm LPe 1V is optimized for ultra-low power, reduced cost and improved design flexibility

MILPITAS, Calif., February 19, 2013 – GLOBALFOUNDRIES today announced additional enhancements to the foundry’s 55-nanometer (nm) Low-Power Enhanced (LPe) process technology platform – 55nm LPe 1V – with qualified, next-generation memory and logic IP solutions from ARM. The 55nm LPe 1V is the industry’s first and only enhanced process node to support ARM’s 1.0/1.2V physical IP library, enabling chip designers to use a single process that supports two operating voltages in a single SoC.

“The key advantage of this 55nm LPe 1V offering is that the same design libraries can be used whether you are designing at 1.0 voltage or 1.2 voltage power option,” said Bruce Kleinman, Vice President of Product Marketing at GF. “What it means is that same set of design rules and models can be adopted, with no extra mask layer or special process required. This translates into cost saving and design flexibility without compromising on the power and optimization features.”

Based on ARM’s 1.0V/1.2V standard cells and memory compilers, GF 55nm LPe 1V enables designers to optimize their design for speed, power and/or area and is especially beneficial for designers who are faced with power constraints in designing System-on-Chip solutions.

ARM offers a comprehensive, silicon-validated platform of 8-track, 9-track and 12-track libraries along with high-speed and high-density memory compilers for GF’s advanced 55nm LPe process.

“The combination of 1V and 1.2V operation along with supporting level shifting logic provides the best combination of low power, high performance and reduced chip area,” said Dr. John Heinlein, vice president of marketing, Physical IP Division at ARM. “Dual-voltage domain characterization support coupled with Artisan next-generation memory compiler architecture reduces dynamic and leakage power by more than 35 percent, compared to previously available solutions.”

The 55nm LPe 1V is especially suited for high-volume, battery-operated mobile consumer devices, as well as a broad range of green or energy-saving products. PDK and EDA tools are available now, along with MPW shuttle availability.
Artisan memories offer flexible manufacturing options and are shipping in billions of products worldwide. Part of a broader platform of Artisan physical IP from 65nm to 20nm, these next-generation memories include low voltage and stand-by modes enabling extended battery life, ultra high-speed caches for maximum processor speed, and proprietary design techniques resulting in reduced area for low-cost SoC designs.

ABOUT GF

GF is the world’s first full-service semiconductor foundry with a truly global footprint. Launched in March 2009, the company has quickly achieved scale as the second largest foundry in the world, providing a unique combination of advanced technology and manufacturing to more than 150 customers. With operations in Singapore, Germany and the United States, GF is the only foundry that offers the flexibility and security of manufacturing centers spanning three continents. The company’s three 300mm fabs and five 200mm fabs provide the full range of process technologies from mainstream to the leading edge. This global manufacturing footprint is supported by major facilities for research, development and design enablement located near hubs of semiconductor activity in the United States, Europe and Asia. GF is owned by the Advanced Technology Investment Company (ATIC). For more information, visit https://www.globalfoundries.com.

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