Uniquify Joins FDXcelerator Program to Deliver DDR Memory IP to GLOBALFOUNDRIES 22FDX® Technology Platform July 11, 2017SAN JOSE, CALIF. –– July 11, 2017 –– Uniquify, a leading system-on-chip (SoC) fabless manufacturer and DDR memory system intellectual property (IP) provider, today announced that it has joined GLOBALFOUNDRIES’ FDXcelerator™ Partner Program.
22FDX® Revving up for Automotive Applications at CDNLive EMEA July 7, 2017By: Gerd Teepe Recently, Cadence hosted its two-day European CDNLive event at a multi-purpose arena in Munich. The arena at the INFINITY Hotel & Conference Resort is also often a draw for ice-hockey tournaments, rock concerts and other high-profile events and visitors. In fact, the Bayern-Munich soccer team has gathered here before important games the last couple of years, bringing further glamour to the area. While the Bayern Munich players did not occupy the arena this year, there was another star attraction at the show—a technical innovation heralding a new era in image processing. Dream Chip Technologies GmbH of Hannover, Germany demonstrated a system with an image processing chip designed and manufactured with GLOBALFOUNDRIES’ 22nm FD-SOI (22FDX®) technology. Dream Chip’s ADAS SoC system platform is based on a quad ARM® A53 processor complemented with a dual ARM-R5 lock-step processor, making the chip suitable for enhanced ASIL-type security applications. The image workhorse of the chip is the Vision-P6 processor from Cadence. Source Dream Chip: Full system architecture of the image processing platform, soon to be implemented by Dream Chip. The Vision P6 architecture from Cadence is based on the Tensilica architecture and is targeted for Convolutional Neural Network computations (CNNs). Image objects are detected by correlation of video images with a database of known images. For applications in the car, like sign- and pedestrian-recognition, this application needs to run at real-time with 30 frames per second. In essence, it’s a massive computational comparison of pictures occurring in real-time. The prototype shown at CDNLive is the first-ever live system with an SoC implemented with GF’s 22FDX technology. The chip is 64mm2 and is mounted on a package substrate together with two LPDDR4 memories. Source Dream Chip: System module with chip and two LPDDR4-memories The Dream Chip ADAS chip is a complex and multifunctional SoC. At CDNlive, Dream Chip demonstrated video capabilities through a system board mounted on top of a model car, with the signal of a hood-mounted GoPro camera fed into the system board. Jens Benndorf, COO of Dream Chip, explained the further signaling path: “First fed into the chip, the video signal is passed to one of the four IVPs running a filter algorithm, then passed to the video-output and on to the display. It demonstrated that the IVP6 is working.” Source GF: Dream Chip live Demo setup at CDNLive EMEA In addition to the demo, Benndorf and his team gave a number of presentations on the system, the chip architecture and the CNN-based image processing for which the chip is targeted in the near future. Dream Chip, GF, and partners are working fast and furious (pun intended!) to accelerate the SoC prototype for production readiness. First silicon was demonstrated in February 2017 at Mobile World Congress in Barcelona, and a video on the platform was showcased at CDNLive in May. What will be next? Ride with us, and find out! 22FDX is enabling innovation in ADAS applications and eventually will for autonomous driving too. By then, Bayern Munich players will certainly notice. About Author Gerd Teepe In his role as Director Marketing for Europe, Gerd is responsible for leading the CMOS Platforms marketing initiatives in this region, with focus on accelerating design wins in the IoT/Industrial and Automotive segments as well as emerging markets. Prior to this, Gerd was leading the Design Engineering Organization of GLOBALFOUNDRIES. Gerd Teepe has been with GLOBALFOUNDRIES since its creation in 2009 and is based at the FAB1-site in Dresden. Prior to GLOBALFOUNDRIES, Gerd was with AMD, Motorola-Semiconductors, and NEC, Japan in R&D, Design, Product Management and Marketing roles. Gerd holds a Master’s Degree and a phd from Aachen University, Germany.
AImotive Releases aiWare: The First of its Kind, AI-Optimized Hardware Accelerator For Autonomous Driving July 3, 2017MOUNTAIN VIEW and SANTA CLARA, Calif., June 29, 2017 – AImotive (www.aimotive.com) today announced its much anticipated, AI-optimized hardware IP is available to global chip manufacturers for license. aiWare, built from the ground up for running neural networks, is up to 20 times more power efficient than other leading AI acceleration hardware solutions on the market. VeriSilicon Holdings Co., Ltd. (www.verisilicon.com), a Silicon Platform as a Service (SiPaaS®) company, will be the first to integrate aiWare into a chip design,and the aiWare-based test chips will be fabricated on the GLOBALFOUNDRIES (GF) 22FDX® semiconductor process (www.globalfoundries.com)
eVaderis加入FDXcelerator™项目，为格芯22FDX®技术平台提供内存IP June 29, 2017eVaderis today announced that it has joined GLOBALFOUNDRIES’ FDXcelerator™ Partner Program to provide scalable, advanced memory IP to be compatible with GF’s 22FDX® technology. The advanced memory IP is expected to offer performance and energy saving advantages over competing memory solutions.
EVADERIS JOINS FDXCELERATOR™ PROGRAM TO DELIVER MEMORY IP TO GLOBALFOUNDRIES 22FDX® TECHNOLOGY PLATFORM June 29, 2017eVaderis today announced that it has joined GLOBALFOUNDRIES’ FDXcelerator™ Partner Program to provide scalable, advanced memory IP to be compatible with GF’s 22FDX® technology. The advanced memory IP is expected to offer performance and energy saving advantages over competing memory solutions.
ICE-P3 能量处理单元（EPU）集成了温度补偿的电压与频率控制，追求最大节能效果 June 26, 2017San Jose, Calif. – June 26, 2017 – Sonics, Inc., the world’s foremost supplier of on-chip network (NoC) and power management technologies and services, today introduced ICE-P3™, the IP industry’s first product to automate implementation of dynamic voltage and frequency scaling (DVFS). ICE-P3 is the newest member of the ICE-Grain™ Family of Energy Processing Units (EPU) that identifies, sequences, and controls power state transitions in hardware up to 500X faster than conventional software-based approaches.
ICE-P3 EPU Integrates Temperature-Compensated Voltage and Frequency Control for Maximum Energy Savings June 26, 2017San Jose, Calif. – June 26, 2017 – Sonics, Inc., the world’s foremost supplier of on-chip network (NoC) and power management technologies and services, today introduced ICE-P3™, the IP industry’s first product to automate implementation of dynamic voltage and frequency scaling (DVFS). ICE-P3 is the newest member of the ICE-Grain™ Family of Energy Processing Units (EPU) that identifies, sequences, and controls power state transitions in hardware up to 500X faster than conventional software-based approaches.
Cadence Custom/Analog and Full-Flow Digital and Signoff Tools Enabled for GLOBALFOUNDRIES 7LP Process Node June 20, 2017Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its custom/analog and full-flow digital and signoff tools are now enabled for v0.5 of the GLOBALFOUNDRIES 7nm Leading-Performance (7LP) FinFET semiconductor technology. The 7LP process node is expected to deliver 40 percent better performance and twice the area scaling than the previous 14nm FinFET technology.
Synopsys and GLOBALFOUNDRIES Collaborate to Deliver Design Platform and IP Enablement for 7-nm FinFET Process June 20, 2017Synopsys, Inc. (Nasdaq: SNPS) today announced the enablement of the Synopsys Design Platform and DesignWare® Embedded Memory IP on GLOBALFOUNDRIES 7-nm Leading-Performance (7LP) FinFET process technology. Synopsys and GF collaboration on the new process addressed several new challenges specific to the 7LP process. This process is expected to deliver 40 percent more processing power and twice the area scaling compared to GF’s 14nm FinFET process. Designers of premium mobile processors, cloud servers and networking infrastructure can take advantage of these benefits by confidently deploying the silicon-proven Synopsys Design Platform and Embedded Memory IP.
