By: Gary Dagastine

By some estimates there are now more than 260 startups and established companies around the world scrambling to develop, qualify and bring to market chips and technologies for new ADAS (advanced driver-assistance systems) and autonomous driving applications.

Accordingly, venture capitalists, technology companies, carmakers, Tier 1 automotive suppliers and others are sharply ratcheting up their investments in this area. Venture capital investments alone in automotive and other AI-based applications grew to some $1.6 billion last year, up from $1.3 billion in 2016 and $820 million in 2015, according to research firm CB Insights.

What’s more, this activity is taking place globally. Among notable recent announcements was the news that Shenzhen, China-based self-driving start-up Roadstar.ai raised $128 million in Series A venture funding. It’s reportedly the single largest investment to date in a Chinese autonomous driving company, eclipsing the $112 million in funding announced earlier this year by another self-driving start-up, Guangzhou-based Pony.ai.

Why is interest in this space growing so strongly? On a consumer level, many drivers appreciate ADAS features like collision avoidance, blind spot warnings, adaptive cruise control and so on, and because carmakers want to satisfy their clients they are working to make these systems more sophisticated and increasingly available in cars at all price points.

On a societal level, driver-assistance/self-driving features have much more to offer. For example, there are about 40,000 deaths from motor vehicle accidents annually in the U.S. and over a million worldwide, with an additional 20-50 million people injured or disabled. Vehicles with greater autonomous capabilities have the potential to significantly reduce these numbers.

They also open up entirely new business opportunities, such as self-driving taxis.

A Brain on Wheels

The standards-setting organization SAE International has established a five-level classification system to describe the level of automation in cars, going from Level 1 (the system gives warnings but the driver drives the car) to Level 5 (fully autonomous operation with no human intervention required).

As the industry moves toward Level 5, sensors such as cameras, lidar and radar will generate torrents of data which must be processed, integrated and transmitted in real-time so that sophisticated deep neural-net-based machine learning algorithms can make use of it to recognize objects in the environment, predict their actions, communicate with other vehicles, and make vehicle-control decisions.

Some argue that this can be best accomplished with decentralized in-car network architecture, because it would be an evolution of existing ADAS systems and therefore would have the least impact on the design of automotive computing systems. It also would accommodate the use of specialized processors and allow new features to be added in a stepwise fashion.

The problems with this approach, according to Mark Granger, GLOBALFOUNDRIES Vice President of Automotive, are that while local processors and limited network bandwidth might be adequate for Level 2 (partial, or “hands-off”) or perhaps Level 3 (conditional, or “feet off”) operation, they lack the ability to handle in real-time the vast amount of data required by AI-based machine learning algorithms to enable truly autonomous operation.

“Decentralized architectures might provide up to 5 TOPs (trillion operations per second) and about 10 Mbits/s of in-car bandwidth,” he said. “But to operate at Levels 3-5, centralized network architecture with powerful, efficient processors that provide 50-100 TOPs and in-car data rates of 100 Gbits/s is needed. To put that in perspective, in the year 2000 the world’s most powerful supercomputer had the ability to do only 1 TOPs. So autonomous vehicles really will have to be brains on wheels, and a centralized architecture is the best way to achieve that.”

Until now the semiconductor technologies at the heart of ADAS/autonomous system development have been graphics processors (GPUs) and microprocessors (CPUs). But as developers move toward Level 5 automation, the proliferation of these chips in automotive systems becomes increasingly problematic, because while they are powerful they are also power-hungry.

“Self-driving cars are in their infancy, and unless something is done to reduce the power consumption of the processors in their AI-based systems, maybe they’ll never grow up,” said Granger. “The chips powering today’s versions of self-driving cars essentially require racks of server-class chips that draw maybe 7,000-10,000 watts of power. While that’s OK for development and testing purposes, it’s impractical for commercial products. Plus, you also have to consider the challenges and expense of cooling them, and they are relatively large physically. Everyone has a goal to get the power budget as low as possible for a given function.”

Enter GF’s ASICs

ASICs (application-specific integrated circuits) specifically designed to meet the needs of automotive systems not only can be both powerful and extremely energy efficient, but they also allow an automotive client to differentiate itself from the rest of the pack. They provide design flexibility and allow for designs that are much more powerful than current GPUs.

Large CPU clusters and hundreds of thousands of multiply and accumulate (MAC) circuits on each die meet the heavy computational requirements of AI algorithms, while gigabits of embedded SRAM and gigabytes of off-chip DRAM interfaces feed the hungry compute engine.

GF offers 14nm and 7nm FinFET ASIC system-on-chip (SoC) devices which deliver optimum combinations of power, size and energy efficiency versus both GPUs and competing ASIC technologies, while meeting automotive quality standards such as the functional safety standard ISO26262.

FX-14™ ASICs allow users to take advantage of an array of 64-bit and 32-bit ARM® cores for system design, along with a 56Gbps high-speed SERDES (HSS); an embedded TCAM memory capable of billions of searches per second; density- and performance-optimized embedded SRAM; and 2.5D packaging options that maximize application flexibility.

FX-7™ ASICs extend the offering with up to 112G HSS, the densest on-chip SRAM and a large number of off-chip DRAM interfaces (LPDDR, GDDR, HBM), including 2.5/3D packaging options that maximize application flexibility.

The GF ASICs differ from those offered by others not just in their capabilities, but also in their pedigree. The IBM Microelectronics acquisition in 2015 brought to GF one of the industry’s leading ASIC development teams, with more than 1,000 design engineers around the world and a history of some 2,000 completed ASIC designs for applications ranging from high-end servers for critical enterprise networks to low-cost gaming platforms.

“Our ASIC team has a proven track record on a range of products from highly complex electronics for servers and aerospace, to high-performance low-cost applications that covered all of the top gaming platforms,” said Igor Arsovski, Chief Technical Officer of GF’s ASIC business unit and GF Fellow.

“Unlike other design houses, we offer a broad array of IP that has undergone systematic and extensive model-to hardware correlation and HTOL stresses to both reduce design-to-tapeout cycle time and improve first-time right design success rate,” he said. “This rigorous methodology has ensured that even after tens of process nodes and over 2,000 ASIC designs we have never failed to deliver an ASIC to our client. Also noteworthy in the automotive context is the fact that our ASIC designs incorporate advanced in-situ testing capabilities, which are critical because high reliability is a prerequisite for automotive.”

Arsovski also mentioned that, since many GF clients vary in their design service requirements, the company offers a full range of packages from full-turnkey service – where the client delivers a spec and requires design center, packaging and test support from GF – to full custom design where the client delivers GDS and only wants fabrication. GF’s agility allows the company to organically support clients as their company and design capabilities grow in the field of automotive electronics.

About Author

Gary Dagastine

Gary Dagastine is a writer who has covered the semiconductor industry for EE Times, Electronics Weekly and many specialized media outlets. He is a contributing editor at Nanochip Fab Solutions magazine and also is the Director of Media Relations for the IEEE International Electron Devices Meeting (IEDM), the world’s most influential technology conference for semiconductors. He started in the industry at General Electric Co. where he provided communications support to GE’s power, analog and custom IC businesses. Gary is a graduate of Union College in Schenectady, New York,

By: Dave Lammers

The last couple of blogs I’ve written have looked at using the 22FDX® technology process for Internet of Things and automotive radar applications, markets that call for a combination of performance at low power consumption. Cryptocurrency mining is another market where power consumption is a defining characteristic, one reason that miners are moving gradually away from GPUs to ASICs.

One of the interesting things about the semiconductor industry is that every application needs a different mix of performance, power consumption, cost, and other factors. The cryptocurrency mining applications are that way, even down to the major coins — Bitcoin, Litecoin, and Ethereum — and the ways they are mined.

Anshel Sag, an associate analyst at Moor Insights & Strategy, who tracks the coin mining market, said miners “don’t want to buy any extra logic on-chip. They want to minimize power. Everything is extremely lean because most of this boils down to power consumption.”

Each of the different algorithms, Sag said, presents “a different bottleneck, and the ASICs need to be architected in different ways to minimize the bottlenecks.” (Sag and Moor principal analyst Patrick Moorhead wrote a white paper on fabs and cryptocurrency miners that provides details on the subject.)

“With so much energy consumed daily, mining operations and manufacturers are always looking at the efficiency of their ASIC miners. Most mining devices ‘performance’ is measured in hashes per watt rather than total hashing capability.” Source: Moor Insights & Strategy White Paper, “The Importance Of Fabs In Crypto Mining”

Architectures Differ

Sanjay Charagulla, senior director of technology marketing and business development at GF, outlined the differences in the miner ASICs optimized for Bitcoin, Litecoin, and Ethereum. The Litecoin ASICs tend to have a relatively small fraction of logic transistors, while SRAM cells account for roughly two-thirds of the transistors. Charagulla argued that GLOBALFOUNDRIES’ 22FDX process has “one of the most efficient SRAM bit cells,” and cited that as a reason why GF has “already taped out multiple customer designs.”

Ethereum mining, which accounts for roughly 10 percent of the total mining IC market, thus far has been dominated by graphics processors (GPUs). The Ethereum algorithm requires a relatively large amount of external memory, and the die sizes are larger. Charagulla said he sees Ethereum mining growing to as much as a quarter of the market, because its overall commercial technology offers good transaction flexibility over Bitcoin.

With Bitcoin – still the dominant cryptocurrency despite a flood of new entries – the mining appliances typically have multiple PCB boards, with each board holding on the order of 50-100+ ASICs. These tiny ASICs are logic devices, with hundreds of multiply and accumulate (MAC) circuits on each die, requiring no external memories or co-processors. And if a couple of cores are not working, the ASIC is able to still grind away. “The Bitcoin ASICs are not that complex. The layout and back end design are key to efficiency,” he said.

With the cost of power so important to miners, efficiency is measured in milliWatts per gigahash, rather than total hashing capability. Bitmain, the dominant mining vendor, has described a 98 milliwatts per gigahash Bitcoin miner, and new competitors are seeking to either match or improve on that. “We have multiple customers engaged, and a handful already taped out, with good results,” Charagulla said.

Good Enough Performance

I asked Charagulla if miners could get to the next space on the blockchain faster by jacking up the ASIC’s frequency and paying for the extra power consumption. He replied that to keep the thermal flow within the miner at an optimum level and conserve power, the smart strategy is to run the ASICs at a “reasonable frequency of 400-500 MHz at the lowest power.”

Even though some Bitcoin ASICs are shifting to FinFET-based processes, Charagulla argued that the better strategy is to keep the manufacturing costs and power consumption down by using the FD-SOI-based FDX process, while maintaining sufficient performance. “The way to do this is to run thousands of cores in parallel, at a certain frequency, so they can still solve the puzzle. The cores are basically a bunch of XOR gates with a 16-bit-wide datapath, in a confined layout. Our belief is that 22FDX will meet the requirements here. Where FinFETs shine is at gigahertz clock speeds, with wider buses and bit-adder logic. In this case (Bitcoin ASICs) there is not any high-speed I/O, so if you can optimize the layout of the cores, FD-SOI can be as good as FinFETs, and at lower costs.”

Many customer designs using the FDX process operate at just 0.4V. Charagulla said one tier one customer is pushing down to a 0.3 Vdd to provide miners with a lower-power-consumption ASIC at 80 milliwatts per gigahash, while “still able to run the algorithm efficiently.” Back biasing and forward biasing can be used to meet the performance and power specs, he added.

Capacity Constraints

Sag, the Moor Insights analyst, said while some “premium” ASIC miners will continue to be made at leading-edge FinFET processes, other miners may take a different tack. “FinFETs on the more-expensive nodes provide higher performance, but at a cost. When the mining ASICs go to smaller design rules, the wafers are more expensive. Right now, people want to drive down the cost of miners, so they can sell more at a lower cost and get more profit. By being on a leading-edge node, such as 10nm or 7nm, the yields are not the greatest initially. The costs are high on a leading-edge node.”

Moreover, mining companies are “jockeying for fab capacity, another reason why the costs are higher,” Sag said.

With GF’s Malta, N.Y. fab running at nearly full capacity at 14nm and the upcoming 7nm processes based on FinFETs, Sag said the mining companies see available 22FDX capacity at Dresden as an opportunity. Moreover, with more than a half-dozen miner device manufacturers based in China, Sag said “22FDX could be used in China relatively soon.”

Sag noted that “GF is doing a good job of choosing the right processes for the right customers, for what is important to them. Not every chip needs billions of FinFET transistors. 22FDX makes sense in terms of price sensitivity, as well as the need for high efficiency.”

The Moor Insights white paper noted that the “GLOBALFOUNDRIES’ FDX roadmap will expand in 2019 and 2020 to include 12nm FDX, which should operate at even lower power and higher performance while also having a cost-friendly profile. We believe this product expansion could significantly benefit miners. The cost of manufacturing chips is becoming an increasingly important factor in their success, particularly as Bitcoin and other altcoin ASIC mining companies aim to turn as much volume as possible.”

Charagulla said the available capacity at Dresden is drawing new miner companies to 22FDX. “Malta is mostly full, and the Dresden fab is clearly positioned for 22FDX, and 12FDX going forward. We are getting design wins in millimeter wave RF, for base stations and mobile handsets and millimeter-wave radar. For the miner ASICs, FDX adds value, and that is why the new entrants are coming to us.”

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.