By: Dave Lammers

A couple of nanometers counts for a lot in today’s semiconductor industry. In an earlier era, foundries would offer a half-node by performing a “litho shrink,” without many changes other than pushing the mask and stepper configuration.

GLOBALFOUNDRIES move to a 12LP process is much the opposite, using the same patterning as on the still-going-strong 14LPP platform but with many subtle changes to the process and standard cell library to achieve improvements in performance, power consumption, and area (PPA). First announced in September 2017, with public support from Advanced Micro Devices (AMD), the details of the process changes came to light in a presentation at the 2018 Symposium on VLSI Technology, held in Honolulu in late June.

On the business side, GF has prepared automotive and RF/analog modules to better support those markets with its 12LP offering. The 12LP process got a major boost last autumn when AMD said it would quickly move major product lines to the 12LP process. Then a mobile customer began using 12LP for its application processors.

Erin Lavigne, deputy director of leading edge FinFET offering management at GF, said “most of the customer interest is in 12LP going forward.” Customers that are designing new ICs go for the higher transistor density, power and performance gains, with cost savings coming from smaller die sizes.

Because the tool set is virtually the same, the manufacturing corridor can be “flexed” for either 14LPP or 12LP production. “Our capacity is fungible,” Lavigne said. “While AMD is a key strategic customer of ours, Fab 8 is not full with just AMD. We can support all of our customers, while continuing to support AMD’s needs. Besides our two lead customers, the pipeline has exploded in fast followers in consumer, AI, automotive, and industrial segments,” Lavigne said.

Hsien-Ching Lo, a GF technology development deputy director, said in one important area — the back end of the line (BEOL) — GF has taken a different approach from its foundry competitors. While other foundries have reduced the M2 pitch to achieve die size reductions, the GF 12LP employs the same 64nm M2 pitch as its 14LPP process. That strategy allows customers to gain in performance, power, and area (PPA) “while minimizing design rework.”

Supporting evidence for that statement came at the VLSI conference in Hawaii. A Samsung Foundry presentation of its 11LP process described an ability to use either a 9T or 6.75 track library. The 6.75T library, however, requires using a 48nm pitch M2, compared with the 64nm M2 pitch of its 14nm process. TSMC has taken a similar tack, changing the M2 pitch for its 12nm offering, which is a follow-on to its 16nm process.

Lo said moving to a different M2 pitch is a design rule change that requires much more design rework than the GF strategy of supporting its 7.5 track library with the same M2 pitch. “It is much easier for our customers to migrate from 14 to 12. They can get a performance and area benefit, with a very small design migration,” he said.

While GF continues to support the 14LPP 9T library for 12LP designs, Lavigne said the 7.5-track library “offers the most bang for the buck” in both die size reduction and higher performance. “There is some redesign for customers to use that library. They can choose how much redesign they want to do to extend the platform.”

Compared with the GF 14LPP process, the 12LP with performance elements delivers a 15 percent faster ring oscillator AC performance, 16 percent less total power for the 12LP (with the 7.5T standard cell library) at equivalent speed, and 12 percent logic area scaling. Notably, the 12LP SRAMs benefit from a 30 percent leakage reduction at the same read current.

Lo took the stage at the VLSI symposium to describe the five process element modifications in the 12LP process.

The fin profile was improved to a taller, thinner fin, improving the drive current and short channel control. Also, the fin surface roughness was reduced, resulting in a carrier mobility increase of 6 percent for the NFET and 9 percent for the PFET.

To improve the PFET performance without increasing leakage, the source/drain cavity profile was modified, moving from a bowl-shaped cavity in the 14LPP process to a deeper cavity in the 12LP process. The enlarged cavity is needed to improve the strain on the channel, delivering more embedded silicon germanium (eSiGe) but without the penalty of higher leakage.

Thirdly, the eSiGe was optimized to improve pattern loading effects, with a 4 percent improvement to the 40-fin devices and a 5 percent improvement to the single diffusion break (SDB) devices.

Fourthly, the NFET doping density was increased. By optimizing the silicon-phosphorus epitaxial process, the source-drain resistance was improved by roughly 6 percent, Lo said.

Contact resistance is a major concern at leading-edge design rules. GF’s Advanced Technology Development team exercised dual optimizations to reduce the contact resistance. The trench contact profile was improved by enlarging the bottom contact size. “We wanted to enlarge the contact area and the bottom CD (critical dimension), but without a penalty in terms of TDDB (time dependent dielectric breakdown). Typically, with an increase in the contact CD, the space between contact to polysilicon gate becomes smaller. Then you can see a degradation in the dielectric breakdown,” Lo said in an interview at the VLSI symposium.

Also, the doping profile under the trench contact was optimized to reduce the contact barrier height. And the silicide resistance was improved by “some interface engineering,” he said.

On the surface of it, going from 14nm to 12nm may not seem to be such a big deal. But scratch the surface, and a lot of engineering work went into delivering a compelling technology.

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.

By: Fisher Zhu

Editor’s Note: This article was previously published in EET China

In Chinese, the use of the word “cooking heat” is not limited to the kitchen; it can also be used to describe someone’s character and maturity.

This also applies to the semiconductor manufacturing industry.

Although a tiny chip looks quite simple, it embodies volumes of scientific knowledge. Only those who truly understand manufacturing processes and application principles know how hard it is to produce a chip, and can appreciate the beauty behind paying attention to small details.

Wafer manufacturing and the cars of the future

Thanks to the unstoppable advancement of semiconductor technology, many incredible automotive functions involving semiconductor technology are being developed; for instance, advanced driver assistance systems (ADAS) are currently paving the way for self-driving cars.

Generally speaking, from now until 2023, the auto applications semiconductor market is expected to grow at a 7% compound annual growth rate, and the market’s value will increase from $35.0 billion to $54.0 billion. Thanks to the impetus from ADAS/self-driving/in-vehicle infotainment (IVI)/electric vehicle powertrain/safety applications, the value of semiconductor chips in every car is projected to rise from $375 in 2017 to $613 in 2025. During this period, the value of the ADAS applications is expected to surge, with an estimated CAGR of 19%.

But in spite of this situation, the vast majority of people are unaware of the increasingly close connection between auto electronics and semiconductor foundries.

IP, process technology, and service are all vital

As for GF’s auto electronics business, the AutoPro™ service package is a critical element. This service package offers the experience, quality, and reliability services for all GF’s automotive technologies. As a result, the service package can satisfy the automotive industry’s strict quality and reliability requirements, and help car manufacturers to use the power of semiconductors to enter the new “smart Internet” age.

The importance of the AutoPro service package solution lies in the way it enables all of GF’s worldwide fabs, including Dresden, Germany; Malta, New York; Singapore; and Chengdu, China, to provide modularized platforms that have passed auto specification certification for various types of automotive clients regardless of which processes they’ve selected to use (e.g., Singapore’s mainstream 180nm, 130nm, 55nm, and 40nm processes, Malta’s 14LPP/12LP/7LP FinFET, or Dresden’s 22nm FD-SOI technology).

Not surprisingly, automotive makers have even higher quality and reliability requirements than clients in other markets. That is why there is a significant importance of having IATF16949 certification.

IATF16949 certification represents confidence that the entire production process is maintained in a controllable, traceable state. It also guarantees that auto-grade IC production, testing, and screening processes have zero-defect status, and is therefore an essential indicator for automotive clients.

GF’s Dresden Fab 1 was recently completed and received its first full-scale IATF16949/ISO9001 certification, which indicates that the plant’s quality management system complies with automotive production requirements, and motor vehicle clients can obtain automotive-specification IC products from GF’s platform.

Selecting the correct process for different applications

Unlike other foundries, GF has entered both FD-SOI and FinFET areas. GF’s 22FDX®, which is part of the AEC-Q100 automotive standard, has already achieved certification, and can satisfy the strict quality and performance requirements of the motor vehicle market.

We have consistently felt that the cost and complexity of the mask process in the production of 22FDX are significantly lower than in the 14nm FinFET process, and the FinFET process also cannot easily achieve the body bias needed by RF devices. As a consequence, by achieving real-time trade-offs between power consumption, performance, and cost, FD-SOI offers an ideal technology for new embedded systems with linking ability. The Internet of Things (IoT), 5G, and ADAS are the most suitable markets for FD-SOI technology. In contrast, an advanced CMOS technology such as FinFET is suitable for chips designed to offer maximum processing performance.

How does one select the suitable process for different applications?

GF has always focused on maintaining close ties with clients and fully understanding their product needs. If a client wants to produce a high-performance processing chip, GF will recommend that they use the FinFET process; if they only want to produce a radar receiver, then the Si-Ge process will be sufficient; and if they want to produce high-resolution radar, the 22FDX process is the most appropriate. And while formulating solutions, GF also helps clients make the right choice by providing PPA analysis reports corresponding to different processes.

Taking automotive radar as an example, the RF unit of current 77-86GHz medium-/long-range automotive radar is usually based on the Si-Ge process, and the digital unit is based on the 180nm and 130nm CMOS process; as a result, the chip’s overall processing capability is poor. In comparison, GF’s 22FDX technology can provide outstanding millimeter wave performance and digital density, which can enable radar sensors based on 22FDX to provide even higher resolution and lower latency, while ensuring extremely low overall system cost. We have seen clients quickly introduce radar imaging chipsets based on 22FDX technology. These chipsets can detect objects within a range of 300 m, and offer a wide field of view with extremely high resolution.

And clients have been using GF’s mainstream CMOS process technology in the development of 77GHz short-/medium-range radar modules. These modules integrate microcontrollers, digital signal processors, SRAM, flash, and support components on individual circuit boards, and can be used to replace large radar arrays.

Of course, radar is only one way that semiconductors are being used in cars. Powertrain control is another way. At the recent Embedded World conference, Silicon Mobility displayed its Field programmable control unit (FPCU), which can be used to control electric and hybrid auto powertrains.

This element was designed to use GF’s 55LPx technology, can process information from and control sensors and actuators in real-time, and can be linked with a standard CPU on a single chip (complies with ISO 26262 ASIL-D safety standards).

A framework based on this FPCU will offer greater functionality, flexibility, and safety, and can boost powertrain control ability and performance in electric and hybrid cars. By employing hardware, not software, to quickly implement complex powertrain control algorithms, this framework can conserve energy and prolong battery life. According to Silicon Mobility, the FPCU can extend the range of electric and hybrid cars by 32%.

At present, MCUs used for air conditioning, engine, and oil system control, short-/medium-/long-range radar, ICs used for electric/hybrid car power supply management, and high-performance processors used in ADAS/self-driving systems account for the leading  shares of GF auto electronics applications services. From our own observations, Chinese automotive clients tend to seek visual and self-driving processing chips, the biggest applications in the European market consist of microcontrollers, sensors, cameras, and lidar, and American clients are targeting lidar and self-driving solutions.

China is a very interesting market, and roughly 30% of semiconductor vendors in the international market are from China. However, many tier 1 auto manufacturers in China still purchase standard radar and processor chips from large motor vehicle device companies—this is the current state of affairs. Nevertheless, GF still sees great promise in the various innovative solutions that have emerged in China; one example of these is the application of visual monitoring system experience to the automotive field. Apart from providing built-in IP solutions such as MIPI interface and Can Bus, our strategy also includes a design center in China to help clients make even better use of GF platforms.

About Author

Fisher Zhu

Mr. Zhu has more than 15 year rich experiences in semiconductor industry. He held various positions in some leading companies, incl. R&D, system design, software and product management and marketing. He is now the China Marketing Director at GlobalFoundries, previously he worked with STMicroelectronics, Freescale and Synaptics.

Mr. Zhu holds the bachelor and master degree of E.E from Shanghai Jiao Tong University.