By: Manuel Sellier

Fully depleted silicon-on-insulator (FD-SOI) relies on a very unique substrate whose layer thicknesses are controlled at the atomic scale. FD-SOI offers remarkable transistor performance in terms of power, performance, area and cost tradeoffs (PPAC), making it possible to cover from low-power to high-performance digital applications with a single technology platform. FD-SOI delivers numerous unique advantages including near-threshold supply capability, ultra-low sensitivity to radiation and very high intrinsic transistor speed, making it perhaps the fastest RF-CMOS technology on the market. On top of these advantages FD-SOI is the only CMOS technology to offer the possibility to fully control the threshold voltage of the transistors dynamically through body bias (Figure 1).

In order to explain why body bias is such a game changing feature we start with the problems it helps to solve. In the search for higher energy efficiency digital designers face two main challenges. The first one relates to the impact of variations, which modifies the actual chip specification defined by the extreme cases of variations (the so called “corners”). This tends to degrade significantly the energy efficiency of the chip (cf. Figure 2). Therefore, to optimize the energy efficiency, product engineers often use compensation techniques (cf. Figure 3). The most common compensation technique is based on Adaptive Voltage Scaling (AVS), i.e. playing with the level of supply voltage depending on the process centering of the chip. This technique is widely deployed in the mobile phone for process compensation but faces severe limitation in automotive and IoT markets because of the strong impact in terms of reliability, the difficulty to implement efficient temperature and aging compensation and the new and specific design know-how that it involves for most design companies.

The second problem lies in the optimization of energy consumption. With advanced technology scaling leakage power has most probably become the most critical problem to solve. It is important to balance correctly the level of leakage with the level of dynamic power. However, in bulk CMOS technologies the parameters fixing leakage (Vth, gate length) are mostly static and defined by process. There is therefore no adaptive leakage optimization possibility, except by switching off entire parts of the circuit. The energy point, i.e. the balance between dynamic and leakage power is fixed and cannot be changed dynamically.

Through its control of transistor threshold voltage, body bias acts as a control knob capable of solving most of these aforementioned issues facing designers targeting energy efficiency.

Not only can global variations be very efficiently mitigated, but also and most importantly, designers can design their chips with reduced design corners for process, temperature and aging, and boosting the Power-Performance-Area (PPA) tradeoff starting at synthesis.

The leakage, which is exponentially dependent on the threshold voltage, can now be modified dynamically with body bias. Energy optimization can be performed dynamically by simultaneously playing with the right amount of supply voltage and body bias. The resulting energy efficiency gain is double at nominal Vdd and can increase to 6x at ultra-low voltage.

To efficiently implement body bias at the circuit level, one must modify current power management infrastructure, which leverages today’s supply voltage only, to support power management solutions capable of managing both supply voltage and body bias.

Dolphin Integration has been cooperating with GF over the past two years to release the world’s first power management IP platform. This power management IP platform, now proven in 22FDX, consists in a consistent set of configurable Voltage Regulators, scalable and module Power Management Unit (a.k.a. PMU logic/ACU), Power IO and island Gating and Voltage Monitors.

To allow SoC designers to extract the full PPAC potential of FD-SOI for their SoC, the companies are now exploring the extension of this power management IP platform to enable the dynamic control of power supply and body bias. This extended power management IP platform will leverage existing body biasing solutions while complementing them with application-optimized body bias generators and advanced monitoring techniques (cf. Figure 5).

The presence of these kinds of solutions available on the market is driving the value proposition for FD-SOI outperforming PPA against any other technology for low power and energy efficient applications. More importantly, the availability of a body biasing turnkey solution lowers significantly entry barriers, making this FD-SOI value proposition available to all players, from mobile and IoT to automotive.

The value of FD-SOI is truly based on the capability to leverage body bias, which is a completely disruptive approach in the advanced CMOS landscape compared to existing technologies. FD-SOI is a game-changer, realizing an order of magnitude power efficiency gain. With the support of silicon IP providers like Dolphin Integration, new power/performance/reliability management infrastructures will be available to customers to fully leverage the benefits of this technology, paving the way to future performance standards in IoT and automotive.

About Author

Manuel Sellier

Manuel Sellier is Soitec’s product marketing manager, responsible for defining the business plans, marketing strategies, and design specifications for the fully depleted silicon-on-insulator (FD-SOI), photonics-SOI, and imager-SOI product lines. Before joining Soitec, he worked for STMicroelectronics, initially as a digital designer covering advanced signoff solutions for high-performance application processors. He earned his Ph.D. degree in the modeling and circuit simulation of advanced metal–oxide–semiconductor transistors (FD-SOI and fin field-effect transistors). He holds several patents in various fields of engineering and has published a wide variety of papers in journals and at international conferences.

By: Manuel Sellier

There is a consensus that “bleeding edge” technologies, i.e. the continuation of Moore’s law whatever the cost of the technology, is bringing less and less return on investment for most players in the semiconductor industry. In this context there is a critical need for more innovations beyond traditional CMOS scaling. There are many opportunities for innovation in the value chain from semiconductor materials and devices to services, but the simplest one starts with substrates.

RF SOI and FD-SOI are great examples of how the industry is pushing differentiation with substrates to develop new standards for RF communication and low power computing. GLOBALFOUNDRIES has been a successful pioneer in this strategy. First, RF SOI has become the de-facto technology for a large number of components of the Front End Module (FEM) in cellular phones. From almost nothing 10 years ago, today the total market for RF SOI is around 1.5 million wafers (8 inch equivalent). Second, FD-SOI is now the technology of choice for mmWave RF-CMOS connectivity and battery powered devices requiring a very high level of energy efficiency. We will review, in this post, how Soitec is supporting GF with outstanding RF SOI substrate solutions.

How SOITEC supports GF with differentiated RF SOI technology

5G will rapidly change the way people and objects around the world communicate; GF and Soitec are supporting this change providing innovative technologies that support the evolution towards 5G and its coexistence with other existent and future standards.

Different communicating devices (vehicles, smartphones, “things”) RF Front Ends require differentiated technologies that could offer the right cost/performance trade-off facilitating their introduction and adoption. Soitec offers two families of RF SOI substrates: HR-SOI using a high resistivity base substrate and RF Enhanced Signal Integrity TM (RFeSI) SOI which adds a trap rich layer on top of the high resistivity base helping deliver on stringent linearity requirements – both of which are compatible with standard CMOS processes and foundries.

These two families of substrates are available in 200 and 300 mm diameters and offer different advantages in terms of linearity, insertion loss, isolation, noise figure and other key specifications and therefore can be used to design and manufacture different blocks and functions in the RF Front End. The examples here below are given as reference only as integration strategy differs largely among different RF Front End solutions providers.

• Antenna tuners, which require very high linearity are typically implemented on RFeSI substrates
• Receiver/ Transmitter switches requiring good linearity, low insertion loss, high isolation and high integration level can be manufactured on HR-SOI and/or RFeSI substrates
• Low noise amplifiers (LNA) on the receive path typically implemented in technology nodes below 90nmare commonly manufactured on 300 mm HR SOI wafers and if integrated with switches and other supporting blocks in 300 mm RFeSI ones.
• Power amplifiers could be fully integrated in 300 mm RFeSi substrates with switches and LNAs for connectivity, IoT and 3G/early 4G cellular applications

Thanks to a long-term strategic partnership GF and Soitec have been timely delivering products tailored to address the needs of a very demanding RF Front End market in continuous evolution.  This partnership extends in many fields including engineering and manufacturing, securing state of the art performance in high volume production.

Soitec is integrated into GF’s roadmap thanks to a shared vision of the market evolution. In the most recent example, GF’s next generation mobile and 5G RF Front End 8SW technology was designed to fully exploit the benefits offered by Soitec’s products.

In a semiconductor world where everybody is looking for differentiation, RF SOI and FD-SOI represent unique platforms delivering major advantages. RF SOI value is now fully recognized. It has been adopted by most of the players in the cellular FEM business. It will see continued growth with the increased complexity of radios at 4 and 5G. Soitec is committed to serve this industry with the right level of capacity and quality.

In our next post we will review how Soitec is supporting GF with outstanding FD-SOI substrate solutions.

About Author

Manuel Sellier

Manuel Sellier is Soitec’s product marketing manager, responsible for defining the business plans, marketing strategies, and design specifications for the fully depleted silicon-on-insulator (FD-SOI), photonics-SOI, and imager-SOI product lines. Before joining Soitec, he worked for STMicroelectronics, initially as a digital designer covering advanced signoff solutions for high-performance application processors. He earned his Ph.D. degree in the modeling and circuit simulation of advanced metal–oxide–semiconductor transistors (FD-SOI and fin field-effect transistors). He holds several patents in various fields of engineering and has published a wide variety of papers in journals and at international conferences.