By: Gary Dagastine

Whenever a company announces a major strategy shift and restructuring, as GF did in pivoting away from 7nm FinFET technology development, it’s understandable that confusion, uncertainty and misunderstandings may arise.

The best way to allay these concerns is to take an objective look at the situation: Demand for chips for the automotive, IoT, mobility and data center/wireless infrastructure markets is growing strongly. That opens up many new opportunities to leverage GF’s broad portfolio of existing, proven technologies by tailoring, or differentiating, them specifically for these markets. In addition, many potential clients in these areas are startups or non-traditional firms that can benefit from GF’s expanding service offerings. Stepping off the hugely expensive FinFET scaling treadmill, therefore, lets GF redeploy its resources to better pursue these opportunities.

Dr. Gary Patton, GF’s Chief Technology Officer and Senior Vice President of Worldwide Research and Development, explained these industry dynamics and discussed GF’s technology strategy in a keynote talk recently at the Global Semiconductor Alliance (GSA) Silicon Summit East 2018 forum in Saratoga Springs, NY. The Foundry Files sat down with him afterward to learn more.

FF: For decades progress in electronics has depended on making transistors smaller to increase the speed and processing power of integrated circuits. What has changed?

Gary: Scaling does still have a place for chips used in high-performance computing, but elsewhere the benefits to be gained by following Moore’s Law are diminishing as scaling costs escalate. That doesn’t mean innovation is finished, though. The good news is that existing technologies are now so powerful that by adding new features to them and combining them in various ways, new architectures and ways of computing are possible. What’s really happening is a shift is taking place, from a general-purpose computing approach to a more industry- or domain-specific one.

FF: How is GF taking advantage of this shift?

Gary: Very successfully, given that a majority of our revenue already comes from differentiated offerings. What we call the four pillars supporting everything we do are our FDX, FinFET, RF and power/analog-mixed-signal (AMS) technologies.

Our FDX technology is purpose-built for today’s power-sensitive applications, offering low active and standby power yet with the density and performance needed. It offers unmatched RF performance for always-on connectivity, low latency, and higher data rates to help make RF-driven IoT a reality. There is a lot of interest from clients designing chips for the IoT, especially as IoT will make a shift in coming years from WiFi- to RF-enabled. Overall we will have about 20 FDX production tapeouts this year, and we expect that number to more than double next year.

In FinFETs, we are realigning our roadmap to serve the next wave of clients that will adopt the technology in coming years. We have shifted development resources to make our 14/12nm FinFET platform more relevant to them by delivering a range of innovative IP and features. For example, for emerging enterprise, cloud and communication applications, we’re working on one-time and multi-time programmable (OTP/MTP) embedded non-volatile memory (eNVM) for ultra-high-security performance. This is based on GF’s physically undetectable and unclonable charge-trapping technology and will make possible market-leading security solutions. They also will offer higher levels of SoC integration. Our NVM solutions require no additional processing or masking steps, and are up to twice the density of similar OTP solutions based on dielectric fuse technology.

In RF, GF has a rich portfolio of offerings that align well with proposed architectures and which continue to advance in order to meet 5G and other requirements. RF FDX, for example, enables deep coverage, massive connections and low power consumption for narrow-band IoT, while RF FinFET technology offers excellent scaling and power consumption. RFSOI enables clients to build state-of-the-art LNAs/switches & control function integration for RF front-end modules, phased arrays, and millimeter-wave beamforming. Our various SiGe-based RF offerings are performance-tuned for a long list of low- and high-power applications including automotive radar/lidar, base stations, wired/optical/ mmWave & phased-array communications. By the way, clients are increasingly using our SiGe-based products with CMOS integration to displace the GaAs processes historically used for cellular and Wi-Fi power amplifiers.

Our AMS offerings span a wide range of process nodes (180-40nm) and voltages (3–700 volts), offering clients an outstanding selection of functions and price points. Our BCD/BCDLite and high-voltage (HV) technologies are based on GF’s efficient HV CMOS process and include power and HV transistors, precision analog passives and NVM memory for a wide range of traditional and emerging mobility, automotive, IoT and other applications.

FF: You mentioned in your talk that advanced packaging is a powerful differentiator for GF.  How so?

Gary: GF’s high-performance, cost-effective 2.5D, 3D, and silicon photonics advanced packaging technologies support each of the four pillars, and are aimed directly at emerging applications like 5G, networking/base stations, AI/ML and advanced automotive solutions.

For example, our though-silicon-via (TSV) technology is well-suited for differentiated uses such as TSVs for RF applications; grounded TSVs for power amplifiers; and isolated TSVs for stacking antennas and/or other passives on RF die (for excellent signal integrity and/or significant size reduction of mobile front-end modules). Also, when implemented through 2.5D and 3D die-stacking, TSVs can allow for reduced latency and power by moving memory closer to logic. Die-stacking can offer significant cost advantages through heterogeneous die partitioning and function re-use like splitting I/O, logic, and memory functions into smaller, lower-cost die using stacking package architectures versus traditional monolithic 2D design.

With regard to silicon photonics (SiPh) ICs, we have both fiber-attach and laser-attach packaging technology that will be offered through GF’s SiPh foundry offerings.

We have been executing qualifications of our advanced package offerings with major OSATs. For 3D packaging, we will support multiple thermal solution options at the OSATs depending on the product thermal needs, I would also like to point out that we have developed test technology for all of our advanced packaging solutions to help clients become familiar with them and speed their projects.

FF: What would you like to say about GF’s research activities now that the company has moved away from extremely scaled CMOS?

Gary: First of all, there was a perception that we were entirely focused on leading-edge research, or that it was the only research that really mattered to us, but that simply wasn’t the case. We have always conducted R&D to bring new features to our existing offerings, to add new capabilities, to increase their performance and/or to decrease their cost. Our FinFET technology provides a good example. First, we successfully integrated a MIM capacitor in the interconnect, which resulted in a 10% performance improvement. Then, we developed new IP libraries and achieved a further 5% boost. Right now we are enhancing the RF capabilities of these proven devices with an eye toward the rollout of 5G.

With the GF pivot, our research focus is to move more aggressively to differentiate our proven technologies—in effect, to create derivatives of them which enable new applications—to address the new opportunities we’ve been discussing.

FF: Where will this work take place?

Gary: We have a large R&D group in Malta whose focus is on differentiated CMOS technology development. Our team in East Fishkill works on silicon photonics, RF and packaging technology, key areas of differentiation for us. In Singapore we have a significant ongoing R&D effort in differentiated power and RF technologies at 40nm and larger nodes, while Burlington is where our industry-leading RF solutions are developed. We continue to collaborate with universities across the world and participate in industry research consortia such as imec, Fraunhofer and IME on a range of topics aligned with what we see as our best market opportunities.

FF: Any closing comments?

Gary: A company is only as good as its people, and I am very proud of our track record of first-time-right client tapeouts across our world-wide fabs. That’s not easy to do with such a complex set of technologies, and is a testament to the talent, professionalism and diligence of our colleagues and engineers.

About Author

Gary Dagastine

Gary Dagastine is a writer who has covered the semiconductor industry for EE Times, Electronics Weekly and many specialized media outlets. He is a contributing editor at Nanochip Fab Solutions magazine and also is the Director of Media Relations for the IEEE International Electron Devices Meeting (IEDM), the world’s most influential technology conference for semiconductors. He started in the industry at General Electric Co. where he provided communications support to GE’s power, analog and custom IC businesses. Gary is a graduate of Union College in Schenectady, New York.

By: Manuel Sellier

Fully depleted silicon-on-insulator (FD-SOI) relies on a very unique substrate whose layer thicknesses are controlled at the atomic scale. FD-SOI offers remarkable transistor performance in terms of power, performance, area and cost tradeoffs (PPAC), making it possible to cover from low-power to high-performance digital applications with a single technology platform. FD-SOI delivers numerous unique advantages including near-threshold supply capability, ultra-low sensitivity to radiation and very high intrinsic transistor speed, making it perhaps the fastest RF-CMOS technology on the market. On top of these advantages FD-SOI is the only CMOS technology to offer the possibility to fully control the threshold voltage of the transistors dynamically through body bias (Figure 1).

In order to explain why body bias is such a game changing feature we start with the problems it helps to solve. In the search for higher energy efficiency digital designers face two main challenges. The first one relates to the impact of variations, which modifies the actual chip specification defined by the extreme cases of variations (the so called “corners”). This tends to degrade significantly the energy efficiency of the chip (cf. Figure 2). Therefore, to optimize the energy efficiency, product engineers often use compensation techniques (cf. Figure 3). The most common compensation technique is based on Adaptive Voltage Scaling (AVS), i.e. playing with the level of supply voltage depending on the process centering of the chip. This technique is widely deployed in the mobile phone for process compensation but faces severe limitation in automotive and IoT markets because of the strong impact in terms of reliability, the difficulty to implement efficient temperature and aging compensation and the new and specific design know-how that it involves for most design companies.

The second problem lies in the optimization of energy consumption. With advanced technology scaling leakage power has most probably become the most critical problem to solve. It is important to balance correctly the level of leakage with the level of dynamic power. However, in bulk CMOS technologies the parameters fixing leakage (Vth, gate length) are mostly static and defined by process. There is therefore no adaptive leakage optimization possibility, except by switching off entire parts of the circuit. The energy point, i.e. the balance between dynamic and leakage power is fixed and cannot be changed dynamically.

Through its control of transistor threshold voltage, body bias acts as a control knob capable of solving most of these aforementioned issues facing designers targeting energy efficiency.

Not only can global variations be very efficiently mitigated, but also and most importantly, designers can design their chips with reduced design corners for process, temperature and aging, and boosting the Power-Performance-Area (PPA) tradeoff starting at synthesis.

The leakage, which is exponentially dependent on the threshold voltage, can now be modified dynamically with body bias. Energy optimization can be performed dynamically by simultaneously playing with the right amount of supply voltage and body bias. The resulting energy efficiency gain is double at nominal Vdd and can increase to 6x at ultra-low voltage.

To efficiently implement body bias at the circuit level, one must modify current power management infrastructure, which leverages today’s supply voltage only, to support power management solutions capable of managing both supply voltage and body bias.

Dolphin Integration has been cooperating with GF over the past two years to release the world’s first power management IP platform. This power management IP platform, now proven in 22FDX, consists in a consistent set of configurable Voltage Regulators, scalable and module Power Management Unit (a.k.a. PMU logic/ACU), Power IO and island Gating and Voltage Monitors.

To allow SoC designers to extract the full PPAC potential of FD-SOI for their SoC, the companies are now exploring the extension of this power management IP platform to enable the dynamic control of power supply and body bias. This extended power management IP platform will leverage existing body biasing solutions while complementing them with application-optimized body bias generators and advanced monitoring techniques (cf. Figure 5).

The presence of these kinds of solutions available on the market is driving the value proposition for FD-SOI outperforming PPA against any other technology for low power and energy efficient applications. More importantly, the availability of a body biasing turnkey solution lowers significantly entry barriers, making this FD-SOI value proposition available to all players, from mobile and IoT to automotive.

The value of FD-SOI is truly based on the capability to leverage body bias, which is a completely disruptive approach in the advanced CMOS landscape compared to existing technologies. FD-SOI is a game-changer, realizing an order of magnitude power efficiency gain. With the support of silicon IP providers like Dolphin Integration, new power/performance/reliability management infrastructures will be available to customers to fully leverage the benefits of this technology, paving the way to future performance standards in IoT and automotive.

About Author

Manuel Sellier

Manuel Sellier is Soitec’s product marketing manager, responsible for defining the business plans, marketing strategies, and design specifications for the fully depleted silicon-on-insulator (FD-SOI), photonics-SOI, and imager-SOI product lines. Before joining Soitec, he worked for STMicroelectronics, initially as a digital designer covering advanced signoff solutions for high-performance application processors. He earned his Ph.D. degree in the modeling and circuit simulation of advanced metal–oxide–semiconductor transistors (FD-SOI and fin field-effect transistors). He holds several patents in various fields of engineering and has published a wide variety of papers in journals and at international conferences.