By: Pat Patla

Information demands are increasing dramatically as digital transformation and other business trends are creating the need for more real-time decision making. Collecting, transmitting and storing the data that helps drive business insights is putting strains on businesses as they grapple with optimizing the increasing flow of data. Nowhere is this taking its toll on traditional systems more than in storage, where both the volume and critical nature of the information is driving rapid changes in how data is handled and tiered. Storage is both the bottleneck of most environments while simultaneously being the most critical component of any application.

Everspin created its nvNITRO™ technology to help address the growing needs for faster and more persistent storage. Built on magnetoresistive random access memory (MRAM) that is fabricated by GLOBALFOUNDRIES, nvNITRO brings both high performance and persistence to data storage, enabling a new generation of application performance.

We recently showed the power of nvNITRO at Supercomputing 17, the worldwide event for high performance computing.

In a demonstration with SMART Modular Technologies, SMART’s NVMe accelerator card was able to drive high performance with ultra-low latency. The demo showed an NVMe accelerator acting as a front-end buffer for an enterprise SSD. While SSDs are transforming businesses today and all flash arrays are gaining popularity because of their performance advantages over rotating media, NAND memory still can’t match the high speed and low latency of MRAM.

Transaction processing is just one of the areas where we see opportunity for MRAM. In these environments, to guarantee the integrity and compliance of transactions, many systems require logging or journaling of each transaction before beginning of the next new transaction. These applications – such as banking, payment processing, stock trading, e-commerce, supply chain, or ERP/CRM – can all benefit from nvNITRO technology. As message traffic increases, that additional logging can become a bottleneck if not handled quickly and efficiently.

With an MRAM storage accelerator as a front end to an SSD, transaction logging can be achieved in a fraction of the time required with just an SSD. The lower latency of MRAM means that these logs can be written faster, freeing the system up to begin the next transaction without delay. nvNITRO’s 9X reduction in latency, through the use of MRAM, means more transactions can be recorded per second, bringing the potential for greater overall application throughput.

The other key benefit that MRAM delivers is its ability to maintain the state of the data without requiring batteries or supercapacitors. For these businesses, writing huge volumes of transactions also presents a second challenge beyond speed – maintaining the data regardless of the state of the underlying system. Typically, when a system loses power or has a power interruption, transactions that are “in flight”, either being written, or being journaled, can be lost because standard DRAM memory is not persistent and the NAND memory in SSDs just can’t write fast enough to capture all of the in-flight data before power is lost. With the persistence of MRAM, this data can be written out faster, reducing the data stored in the buffer. If the system does need to restart, that data would still be persistent in the MRAM upon initialization. In a world where regulatory entities scrutinize every transaction and may need a financial company to “replay” its transactions, ensuring everything was logged properly the first time is invaluable. This sort of protection goes beyond just protecting the data; at that point, it is actually protecting the company.

The traffic at Supercomputing was brisk and we were happy to see the level of excitement that our demo was producing. Technology like MRAM can become a great foundation for many future platforms. The ability to integrate nvNITRO technology into storage solutions through a variety of interfaces – directly as a PCIe or U.2 device, integrated into the chassis or integrated directly into the system boards – means there is a wide variety of implementations to match specific needs. Discussions about nvNITRO always start with the specific use case being shown, but eventually becomes “hey, could you…?” And that is where it gets interesting.

Along with the STT-MRAM that we were displaying in the nvNITRO demo, STT-MRAM is also available as embedded MRAM (eMRAM) through GF for those applications that demand the persistence, durability and write performance that embedded flash (eFlash) cannot deliver. As we see growth in areas like drones, IoT and autonomous vehicles, the value of embedding MRAM directly into designs will grow. Today’s nvNITRO solutions are built on Everspin 40nm STT-MRAM technology that is produced by our partner GF. Additionally, GF is now offering process design kits for 22FDX eMRAM. GF expects customers to start prototyping MRAM on multi-project wafers (MPWs) to start in Q1 2018.

We see the immediate opportunity today in accelerating the storage of massive data streams. These large amounts of telemetry need to be efficiently handled in a manner that ensures both fast capture and long-term retention. But as MRAM and eMRAM continue to gain market momentum (moving traditional memory and storage products aside) and the form factors shrink, we will see even greater opportunity present itself. Today we are accelerating the back-end storage and processing piece of the equation but it is not a stretch to see MRAM and eMRAM potentially integrating into the front-end and edge devices that are creating this data – and that is where things begin to get even more interesting.

If Supercomputing 17 was any indication, the future is bright for MRAM.

By: Timothy Saxe

Embedding FPGA technology into SoC designs isn’t really a new idea.  In fact, at QuickLogic we’ve been doing it for nearly two decades, starting with our FPGA/hard PCI controller SoC all the way back in 1999.  The value proposition was the same then as it is now.  Higher levels of integration delivering a higher level of functionality, performance, and design flexibility with lower cost, power consumption, and board space requirements.  So why hasn’t eFPGA technology taken off much sooner?

The answer lies fundamentally in the relationship between die costs and development costs.  Let’s start with die sizes and costs.  Our PCI device in 1999 employed a 0.35 micron process which used 24,650 square microns per logic cell.  By 2002, the 180nm process we used for our QuickMIPs device resulted in 9,306 square microns per logic cell – less than half the area for more FPGA capability.  Today our latest device, the EOS™ S3 Sensor Processing Platform, includes an even greater level of FPGA capability with a die area of just 961 square microns per logic cell through the use of a 40nm process technology.  That’s roughly a factor of 25 reduction in the die area of the eFPGA portion of these devices over the last 18 years.

Lower die area requirements for eFPGA technology mean that it can be integrated into an SoC with only a very minor increase in total device cost.  For example, we estimate that in a device built using 40nm process technology, adding 1,000 logic cells of eFPGA capability to a 3mm x 3mm die only increases the total die size by roughly 10%.  The corresponding cost increase will be slightly higher or lower percentage-wise depending on die yields and package costs, but the cost increase for such a device is marginal.  Given all of the benefits we described earlier, the value proposition from the device perspective now looks really compelling.

Let’s continue on to take a look at development costs.  More advanced process technologies are more expensive to develop and require more sophisticated design and verification tools which cost more money and require the SoC designer to invest more time in the design cycle.  Making a design error, or getting a feature wrong, or trying to deliver a product extension, or address a group of fragmented but related market opportunities, or keep up with rapidly evolving market requirements all create the need for additional mask spins and that costs significantly more money now than it did ten or twenty years ago.

In today’s world of highly complex SoCs the reality is that the silicon is cheap, but development is expensive.

So what’s a thrifty developer to do?  The answer is to embed a reasonable amount of FPGA technology.  There will be a relatively small incremental silicon cost, but they will gain the ability to leverage their high investment in development by adding a high degree of post-manufacturing design flexibility.  Instead of needing expensive design and verification mask spins to fix bugs, change features, or address new market opportunities or rapidly evolving standards, they will keep the “hard-wired” portion of their device intact and simply update the programmable FPGA portion.  In fact, we estimate that a company can very easily save 40 percent in development costs for two variants of the same design through the use of embedded FPGA technology.  And that doesn’t include the higher peak revenue levels, gross margin dollars, and longer time-in-market benefits associated with having the right product in the market at the right time.

eFPGA technology is a particularly great fit for SoC designers working with GLOBALFOUNDRIES.  The new 22FDX® process delivers strong economic benefits for new devices, with fewer masks required compared to previous generation nodes. Its dynamic back-bias feature reduces power by an estimated 78 percent (@0.6V) relative to 40nm processes.  That makes it well-suited to the low power and ultra-low power wearable, hearable and IoT applications which our eFPGA users are targeting.

So, if you are an SoC developer or manager, the bottom line is that lower development costs and higher profits are yours for the taking through a combination of QuickLogic’s eFPGA technology and GLOBALFOUNDRIES’ 22FDX process. The time is now.

 

By: Mark Granger

The automotive market for semiconductors is shifting into high gear. Right now the average car has about $350 worth of semiconductor content, but that is projected to grow another 50 percent by 2023 as the overall automotive market for semiconductors grows from $35 billion to $54 billion.

This strong growth is being driven by the need to develop what we are calling the ‘connected car.’ The term refers to the multiple electronic systems in a vehicle that collectively take data from wired and wireless sensors and combine it with high-performance processors and analog/power semiconductors, to provide the vehicle with semi-autonomous and ultimately fully autonomous capabilities.

These capabilities include Advanced Driver Assistance Systems (ADAS) such as collision and blind spot warnings, sophisticated infotainment and telecommunications options, and precise electrical control of major vehicle subsystems like the powertrain, among many others.

The move toward the connected car is driving fundamental change in the automotive supply chain, which is presenting GF with a unique opportunity. Traditionally, there have been separate and distinct tiers of automotive suppliers. At the top of the supply chain are the automobile manufacturers themselves, known as the original equipment manufacturers, or OEMs. Tier 1 suppliers such as Bosch, Continental, Delphi, etc. supply automotive-grade parts and systems directly to the OEMs.

Tier 2 is where we have always fit in. Tier 2 suppliers such as semiconductor companies have traditionally supplied the Tier Ones with parts for automotive systems, and have tended not to work directly with the OEMs. However, this is changing. As more electronics-based systems are used in automobiles and as they become more complex, there is a greater need to understand system architectures and networks, and to bring complex IP and quality standards to the design and manufacture of the SoCs and other chips that meet those needs.

That is exactly what we do here at GF. It’s why we recently announced a platform called AutoPro™ that provides OEMs and other automotive customers with a broad set of technology solutions, design and manufacturing services that help them implement connected intelligence while minimizing certification efforts and speeding time to market.

AutoPro is built on our 10 years of automotive-industry experience and leverages GF’s diverse technologies for automotive customers. It includes our silicon germanium (SiGe), FD-SOI (FDX™), RF and advanced CMOS FinFETs, packaging and intellectual property (IP) technologies.

Importantly, it also includes system-level architects who work directly with OEMs. In recent years GF has hired many people with extensive automotive SoC experience, such as myself, and the networking system designers in our industry-leading ASIC business from the IBM Microelectronics acquisition are unparalleled.

AutoPro solutions support the full range of AEC-Q100 quality grades from Grade 2 to Grade 0, and, in addition, we ensure technology readiness, operational excellence and a robust automotive-ready quality system through our AutoPro Service Package.

This gives customers access to the latest technologies designed to meet strict automotive quality requirements defined in the ISO, International Automotive Task Force (IATF), Automotive Electronics Council (AEC), and VDA (German) standards.

Although AutoPro was only recently introduced, we are already at work with automotive OEMs.  One that we can mention is Audi, which has called our automotive offerings essential for delivering next-generation car electronics faster and with high reliability.

It’s early days, but the road is open before us.