by Gary Dagastine

As integrated circuits (ICs) become more complex and vital in applications where failure can’t be tolerated – such as automotive – the ability to accurately model and verify a proposed IC design’s performance and reliability in a given application has taken on urgent importance. This ability is critical to achieving first-pass successful silicon, and it is why that humble workhorse, the process design kit (PDK), now finds itself in the spotlight.

The PDK is a collection of files which describe the details of a semiconductor process to the EDA tools used to design a chip. Clients use a foundry’s PDKs prior to production to ensure that the foundry can produce chips based on their designs, and that they will work as intended.

GLOBALFOUNDRIES has a major effort underway to ensure that its PDKs give clients an unrivaled ability to quickly and cost-effectively create ICs optimized for applications where GF’s differentiated technology platforms offer unique advantages.

“PDKs are the primary interface and the most important touchpoint a client has with us, because if the client doesn’t see a way to achieve its power, performance and area (PPA) goals within a GF PDK, then they’re not going to engage with us in the first place,” said Richard Trihy, GF’s vice president of design enablement.

“Last year alone we released hundreds of different PDKs, which is a testament to GF’s highly differentiated and feature-rich solutions,” he said. “But given that a PDK can be hundreds of gigabytes in size, and may have tens of thousands of individual files, our goal also has been to make them more nimble, interactive, and easier to download and use, with standardized interfaces across our diverse technology platforms,” he said.

Led by Trihy, GF’s focus on PDKs over the past year has benefited from initiatives on multiple fronts. These include expansion of the size and capabilities of GF’s design and engineering teams, which are available to work with customers throughout the design process; strategic investments like the acquisition of the 125-person PDK engineering team from Smartcom; development of differentiated PDK features that are matched to application requirements; and growth of GF’s partner ecosystem.

So What’s in a PDK?

In a GF PDK you will find:

• Technology files that describe the relevant design rules, along with design rule checking tools;  
• Parameterized cells, or PCells, which describe the possible customizations of  transistors and other devices) which are available to designers in the EDA tools;
• Parasitic-extraction and layout-versus-schematic decks that describe a semiconductor, so that an EDA tool can recognize devices in a layout and generate accurate representation in a netlist;
• Device models that describe the electrical behavior of all the passive and active devices (i.e., transistors) to be used in a simulation. 

There are many other component tech files in the PDK such as place-and-route, fill decks, EM/IR, electromagnetic simulation and specialty EDA tools that need additional enablement. In addition, multiple EDA vendors provide competing tools, and part of the job of GF’s Design Enablement organization is to enable all of those tools that our clients need.

“Two key elements are critical to our design enablement and PDK delivery,” Trihy said. “The first is quality assurance, or QA. The PDK QA team verifies not only that each component of the PDK is correct, but that the interfaces between the tools and the overall design flow is correct. 

“The second key element is a collection of reference flows and design guidelines, which are essential in representing how the design flow works and for providing recommendations to our clients to get the best results with the PDK,” he said. “As part of a reference flow, our team collaborates very closely with EDA vendors to ensure all key features enabling GF’s differentiated technology are supported in the tools.

Trihy explained that as chip designs increase in functional complexity, guidance on design methodology becomes increasingly important. Reference flows for highly integrated SoC designs are needed which incorporate transceiver, compute, analog, and non-volatile memory blocks.

“Enabling block-level co-design together with 2.5D/3D packaging is emerging as a competitive foundry differentiator, and EDA vendors play a key role as development partners to expand the PDK horizon beyond the chip-level,” he said. “Signal integrity and thermal management drive co-design methods and supporting CAD tools, which must comprehend a diverse range of operating conditions up to millimeter-wave frequencies. This is a very active area of development which will create new content and structure in our PDKs over the long run. Such challenges place new demands on documentation and guidelines which sustain ease-of-use.”

Peter Rabbeni, vice president of GF’s Mobile & Wireless Infrastructure business unit, said, “We work closely with our ecosystem partners to ensure that GF’s PDKs interface seamlessly not only with design software from leading EDA vendors but also with other commonly used third-party toolsets. For example, clients have many options when it comes to choosing an electromagnetics simulator, which is critical for the design of mmWave ICs. Our ecosystem partners work closely with us to integrate them into our PDKs.”

A Deep Dive Into Reliability

Designers of today’s complex, highly integrated ICs face many challenges, given that mission-critical applications require a much deeper analysis of IC performance and reliability than is typical with chips destined for more traditional data-processing applications.

Accurate modeling is key because variability in materials, processing and packaging – along with the impact of secondary electrical effects such as parasitics and accelerated aging – have a major impact on reliability. If a PDK is incapable of allowing a designer to adequately model the effects of variability on a design, then the chip which is ultimately produced based on that design may not work as intended under all conditions, and/or it may age prematurely and fail unexpectedly.

In addition, the foundry’s PDKs must ensure there is good model-to-hardware correlation (MHC), so that what clients simulate is what actually gets built. “First-pass success in silicon is always the goal because the faster a client’s chip can be qualified, the lower its manufacturing costs will be and the faster it can get to market. However, across the industry, qualification failures continue to be a huge problem,” said Kenneth Barnett, director of GF’s corporate application engineering group.

“We’ve worked hard to become a leader in first-pass success, and we now offer superior MHC results, based on the industry’s best RF, reliability and thermal coupling models,” he said. “We’ve also created a number of reference flows that add to our first-pass success rates by helping clients better understand how to design ICs for complex applications using GF’s differentiated technologies. These reference designs have been built using various GF technology platforms; among them are our 45RFSOI solution for 5G/mmWave and SatComm applications, and our 22FDX® FD-SOI solution for mobile processors and the wireless networking, IoT and automotive markets.”

GF is also continually adding innovative IP to its PDKs. A case in point is GF’s 90nm 9HP SiGe solution. Adam DiVergilio, technical expert on GF’s design enablement team, pointed to a new algorithm GF developed that enables designers working with the 9HP platform to make reliability-based simulations for libraries of highly complex models. “Our ecosystem partner Cadence incorporated support for our architecture into its RelXpert reliability simulator, and as a result we are now able to more efficiently support reliability simulations in our SiGe PDKs.”

Unique Advantages for RF/mmWave

GF’s 22FDX platform can fairly be called the “Swiss Army Knife” of chip technology because of its versatility, according to Barnett. “22FDX offers users substantial processing power, and its back-biasing capability enables it to be tailored for either high performance or low power uses, making it well-suited to diverse applications that require analog/mixed-signal SoCs, hence the nickname,” he said. “Therefore, we have to provide our clients with the best PDKs possible so that they can take full advantage of these features.”

He gave the example of modeling and verifying IC designs in 22FDX for RF/mmWave applications. These are among the most difficult applications to fully understand given the complex physics involved, but they represent a core competency for GF, based on the decades of experience gained with the IBM Microelectronics acquisition.

“The proprietary GLOBALFOUNDRIES IP embedded in our PDKs enables clients to create far better solutions than they could anywhere else,” Barnett said. “For example, in wireless communications applications, the PDKs for use with GF’s 22FDX platform enable clients to create solutions where the power amplifier (PA) is integrated with the front-end, which results in higher output power, lower LNA noise, and a dramatically improved link budget.”

Peter Rabbeni said the quality of GF’s models for RF/mmWave applications is unmatched. “We characterize our models well above typical operating frequencies, up to 110 GHz, because it is important to capture device operation at these high frequencies. We use a proprietary methodology which we have developed over many years, and we leverage physical test sites that enable us to correlate our models with actual measurements in a process of continuous improvement.”

As a result, he said, GF’s PDKs are enabling clients to adapt more easily to seismic shifts in RF/mmWave design that are taking place. One example is newer massive MIMO and phased array systems for 5G infrastructure, which use multiple power amplifiers and signal chains to aggregate and develop the radiated energy signal rather than a single signal chain that we have seen in previous systems. This new approach to the development of radiated power now makes silicon a very powerful contender against GaAs or GaN-based systems since the power is distributed across many elements rather than just a single element.

“The ability to extract the best performance from the array requires a client to know how much each element can be driven, but if you didn’t have the benefit of accurate reliability and lifetime models that are available in our PDKs, you might be forced to operate a PA device at less than ideal conditions to ensure its reliability,” Rabbeni said. “And in that case, one might need to overdesign the system with many more PAs, at much greater cost, and with a much higher power budget in order to achieve the desired performance.”