Foundry Files Guest Blog

This article originally appeared in The Chip Insider, August 7, 2015, and is printed here with permission from VLSI Research, Inc. GLOBALFOUNDRIES’ 22FDX is the first radically new process since Intel introduced the first working finFET process. You may have noticed an omission on my part for some time. That is I’ve never written much about FD SOI over the years. The reasons are pretty simple. First, I didn’t have anything positive to say that I really believed. The problem with FD SOI has been that it’s only salable advantage was that it was cheap. And even that was in question, because the big dogs didn’t bite — and they’re all about lowering cost. Even if it was cheaper, no fabless company is going to risk its future on lower wafer costs. The upfront NRE costs of a new design, time-to-market constraints, as well as the consequences of failure should it not yield, overwhelm the promise of cheaper wafers. The giga-fabbed chip makers know this, so they won’t move until their customer moves. That’s all changed with 22FDX. The big advantage of 22FDX is the ability to have real-time trade-offs between power and performance via software-controlled body-biasing of the transistor. Yes, there are real time power consumption trade-offs that can be made at the device level — mostly by turning on-and-off major functional blocks. But to the best of my knowledge it’s never been at the transistor level on a market-worthy process. If this works like they say it does, 22FDX will be a major revolution that will be disruptive throughout the electronics industry. Here’s why: Imagine a future where you could set how many hours your battery will last. Right now, the best thing an OEM can do is shut certain functions off as power dwindles, such as how the Apple WATCH does. But with 22FDX, you could potentially set your watch to something like, ‘run until 9 PM, when I expect to take it off.’ And then change it to later or reset it the next day if you wanted. Then the watch would match its power-performance trade-off to a prediction based on your typical use and then modify its performance based on how you’re using it that day. It would work the same way on phones, laptops, and just about any mobile electronics you can think of. Now how cool is that! This guest article was written by Dan Hutcheson, CEO and Chairman of VLSI Research Inc. Hutcheson is a recognized authority on the semiconductor industry, winning SEMI’s Sales and Marketing Excellence Award in 2012 for “empowering executives with tremendous strategic and tactical marketing value” through his e-letter, The Chip Insider®; his book Maxims of Hi-Tech, and his many interviews of executives. Dan’s public work on the industry includes two innovative articles for Scientific American challenging predictions of the demise of Moore’s Law by demonstrating how scientists’ innate abilities to innovate have outpaced the doomsayers and an invited article on the history and economics of Moore’s Law for the SIA.

In our journey at Fab 8, we’ve made great strides. Last year, we crossed a significant milestone – moving from construction to full-scale production, and driving to ramp the early-access version of our 14nm FinFET technology (14LPE) to volume production.

This year we have driven a steady march of execution with our performance-enhanced 14LPP technology. We kicked off the year with the exciting news that our 14nm technologies will be fueling some of the most powerful compute and graphics applications, with AMD’s new lineup of discrete graphic processors.

Continuing this momentum, we delivered strong technical results by reaching mature yields in high volume production on multiple products, introducing several new products for major customers—including complex chips with very large die—and achieving a 100 percent track record of yielding first-time-right silicon and aggressively ramping production to support product launches.

It is our relentless focus on execution that is now allowing our customers to differentiate their products, and to bring them to market on time. Another great example is the latest news from AMD, who recently gave a performance preview of its next-generation “Zen” processor core. Just like AMD’s newly launched Polaris graphics chips, this processor is built on GLOBALFOUNDRIES’ 14LPP process technology. It is the powerful combination of AMD’s design expertise and GF’s 14nm FinFET technology that allows Zen to deliver a landmark increase in processor performance over previous generations.

I am pleased to report that customer traction remains strong across a number of segments, with more than 20 active engagements in the mobility, consumer electronics, and high-performance computing sectors. And the interest is not just from traditional foundry customers, but also from companies that are looking to take advantage of the capabilities provided by our FX-14™ ASIC offering for cloud networking, wireless base station, compute, and storage applications.

Looking ahead, we are committed to delivering leading-edge technology platforms, while enhancing our 14nm FinFET technology, to enable new opportunities and secure a strong foundation for future success, including 7nm next generation technology.

By Dave Lammers

Packaging has emerged as one of the semiconductor industry’s most potent forms of innovation. As classical (geometric) scaling has become more difficult, various “equivalent scaling” innovations have stepped up to the plate, notably 193nm immersion lithography, strained silicon, high-k/metal gate, finFETs, fully depleted SOI, and vertical NAND.

Now it is packaging’s turn, and that puts the spotlight on experts such as Dave McCann, the vice president of packaging research and development at GLOBALFOUNDRIES.

In an interview at his office in Malta, N.Y., McCann said more customers are turning to packaging innovations. “In all application spaces, customers are, more than ever before, integrating multiple chips in one package to address scaling limitations,” he said.

For high-bandwidth applications such as servers and networking, McCann said GF is the only foundry to have 32nm TSVs in high-volume production.

GF and Micron Technology have worked together on Hybrid Memory Cube (HMC) products, with GF creating the TSV-enabled logic layer which is stacked with Micron’s DRAM chips.

“We are getting a lot of customer requests for 2.5D design, which take advantage of our experience in ASICs plus memory and high-speed Serdes. Most of these are on silicon interposers, on which we create high density traces to interconnect the ASIC and memory, so that customers achieve very high bandwidth products.” 

RF and IoT innovations are also driven by multi-chip applications, utilizing chips from different GF fabs and nodes. This enables use of chips at the most cost efficient node rather than forcing integration and suboptimum costs, he added.

One intriguing R&D thrust for some RF and IoT applications is to use glass substrates, instead of silicon, which can be too lossy. “We believe we can create very dense interconnects, and get rid of all of the passives, using through-glass vias. Products could become much thinner,” McCann said. Photonics is another important area. The goal is to bring photonic signals directly to the module, instead of stopping at the board or backplane.

For upper-end mobile and other markets, McCann said “wafer-level fan out is a terrific technology first for enabling more IO. Later we will see it used also for integrating multiple chips, starting with the memory and apps processor.” High density fan-out applications will cost more than the low cost substrate-based packages they will replace, however.

Thin glass and FO-WLP allow multiple chips to be placed very close together, providing for a much smaller footprint, thinner profile, and higher performance. The profile is thinner because the laminate substrate is eliminated. And McCann noted these technologies are “particularly interesting for RF and IoT, because of the low loss for high frequency signals.”

“The lowest cost WLFO supply chain will utilize OSATs for what they do best. We do not want to do what an OSAT can do just as well, or better. Especially in the mainstream technology areas, OSATs can offer their solutions to many customers, more cheaply than we could internally,” McCann said. He added that this gives customers the flexibility to use the supply chain they want to use.

“The combination of GF with IBM’s Microelectronics division brings new opportunities, including high-density stacking applications. Being the only Foundry with HVM experience on high-density 3D TSV in logic, we bring credibility to the marketplace,” McCann said. In addition to TSV’s in 3D, GF designs and develops 2.5D silicon interposer products in-house for volume manufacturing at OSATs, “providing the best combination of design skills with a low-cost production path.”

“GF is also working on low-cost alternative memory technologies that will scale with new silicon nodes at no added layer cost and technologies for use in multiple product technologies,” McCann said. GF portfolio scales across both 2.5D as well as 3D packaging solutions

Industry analysts said they are keeping a close eye on the foundry’s packaging skills.

Dick James, senior fellow at ChipWorks (Ottawa) said GF has an opportunity to further leverage the through-silicon via and interposer technology developed within IBM Microelectronics over the last decade. James noted that the recently released executive summary of the International Technology Roadmap for Semiconductors (ITRS) emphasized the need to integrate heterogeneous ICs in system-in-package solutions. Putting together high-bandwidth memory with graphics processors is a particularly important area going forward, James said, one that will take advantage of the interposer experience at the GF Fishkill, N.Y. fab. McCann added that this also will build on GF’s expertise in large thin die stacking.

Jan Vardaman, president of the Austin, Texas-based packaging consultancy TechSearch International, said her firm is seeing increased uses of silicon interposers for high performance applications. “The use of a silicon interposer allows the use of a heat spreader on the top to help remove heat,” she noted.

The use of wafer-level fanout packaging is also bringing a lot of infrastructure changes, Vardaman said, starting with IC/package co-design.

Thus far, most application processors had been using a laminate substrate with flip chip interconnects. “With fan out WLP there is no need for a traditional laminate substrate with underfill. There are just a lot of infrastructure changes. All packaging can take place at the foundry, or at an OSAT which has a non-traditional OSAT assembly line,” Vardaman said.

TechSearch is seeing a rapid adoption of FO-WLP beyond its widespread use in baseband processors, to RF transceivers and switches, power management integrated circuits (PMICs), automotive radar modules, near field communications (NFC), audio CODECs, security devices, and microcontrollers.

GF collaborative supply chain model for 2D, 2.5D and 3D interconnect

It’s no wonder, then, that customers are beating a path to Dave McCann’s office. McCann said “the number of customer engagements is multiplying,” attracted by the mix of OSAT partners and internally developed technologies.

“GF does not ever plan to be an OSAT. But where the OSAT is not investing, where we can develop unique capabilities internally and gain a differentiating advantage, then we will partner with an OSAT to ramp that solution into production,” McCann said.

Lately, there’s been a lot of buzz about silicon photonics in the data center industry. What’s it all about? The ever-expanding digital universe is being driven by cloud computing, mobile data, video streaming, and Internet-of-Things (IoT). Today, it’s estimated that by end of 2016, more than 6 zettabytes (i.e., the equivalent to about 250 billion DVDs) of data will be pushed through data centers and this number is expected to double by 2020. Moreover, networking bandwidth is doubling every two to three years, meaning that the number of links and each link data capacity is doubling – 10G is becoming 25G, and 40G ports are evolving to 100G ports. Moving all of this data within data centers (between the servers, switches, and storage) will require the widespread adoption of optical communications in order to scale with the growth in storage and computing demands. Using copper wires and fiber-optic technology to transmit the digital information will not keep pace with Moore’s Law.

For a long time the photonics industry has been working on hybrid silicon technologies such as indium phosphide and silicon germanium. Fast forward to today: traditional CMOS fabs have been able to successfully manufacture Photonics IC and optical components without special processing steps and additional associated costs. Laser technology has also evolved different fiber technologies (SMF and MMF), supporting multiple wavelengths operating at 1550 and 1310 modes.

For data centers, this helped create momentum for longer-reach, fiber-based connections to overcome copper’s limitation of 100 meters. The optical connections address the up to 2km reach within data centers and up to 80km outside data centers. Finally, technology analysts are projecting huge growth for SiPh-based modules, lasers, and fiber deployments, with two big markets driving the momentum: Datacom and Telecom, which are creating new markets in Data Center Interconnect (DCI), Metro Area, Content Delivery Network (CDN), and Basestation Front haul markets. Thanks to the hyper-growth in cloud data center traffic and the transition to 400G in the optical transport network, cloud data center giants are claiming that they will consume three-fourths of the optics in the entire world by next year. That means SiPh-based 100G ports will be ramping to multi-millions per year starting in 2017.

Additionally, growth in the number of servers deployed has skyrocketed to more than 12M per year, and connectivity from rack-to-rack, rack-to- switches, and switch-to-switch are morphing to fiber-based connectivity in order to meet the networking bandwidth for power hungry data centers with lower total cost of ownership (TCO).

This makes me eagerly optimistic about on-board optics, PSM4, QSFP56, and CFP4 type modules and form factors.kets driving the momentum; Datacom and Telecom, which are creating new markets in Data Center Interconnect (DCI), Metro Area, Content Delivery Network (CDN), and Basestation Front haul markets. Advancements in SiPh technology are essential for data center speed. A recent Cisco VNI update estimates that traffic between DCI to DCI is equal to the 1/7th of the traffic inside data center. What that mean is DCI to DCI and Metro links will be screaming for the bandwidth and dense connectivity of 100G links in the near future. For all the obvious reasons, SiPh chips are the right choice to lower the cost and power consumption, while improving bandwidth and capacity. Remarkably, Metro and CDN networks will become key enablers for advancing silicon photonics technology.

Source: Cisco Global Cloud Index: 2014–2019

Content providers, network operators, and content delivery networks are seeing tremendous growth fueled by video streaming and overall broadband access and backhaul networks. This insatiable bandwidth need is driving video streaming networks to move to multi-100G based SiPh solutions. Especially in the long-haul, transport networks will see the need for multi-100G line rates, 400G, and up to 1.2Tera bits transponders and muxponders line cards. A few optical companies have started demonstrating 200G based solutions in this area, creating a great opportunity for optical component vendors, module manufacturers, and silicon photonic chip manufacturers. The growth ladder for silicon photonics is coming from the new 5th generation, 5G technology for cellular systems. The real question is: why is 5G driving silicon photonics’ inflection point? Wireless infrastructure pundits are claiming 5G is a panacea technology and it will support 10G/s bandwidth, 1000x capacity at lowest round trip latency ~1ms, in comparison with LTE technology. Top infrastructure vendors like Ericsson, Nokia and Huawei are vigorously looking for new architectures to fulfill the 5G dream with bandwidth requirements at the lowest TCO. Some key trends are large-scale array antenna and mm-wave communication with many remote radio heads (RRH) deployed in the field (small cells again!). In the front haul, all these remote radio heads are connected to a centralized radio access network (CRAN), referred to as the super basestation (should I say virtualized?). Since these basestations are isolated from each other, with kilometers of distance, they require a high speed, and reliable connectivity networking. This is where the need for OTN based Silicon Photonics connectivity comes in, when 5G basestations deployment ramps, infrastructure growth will explodes and China alone will have millions of ports and volumes with Silicon Photonics. But in reality, 5G deployments are bit far away, meaning they will probably not begin until 2018 and beyond (and more likely 2020+). But clearly 5G front haul architectures will propel the demand for various silicon photonics modules and chip sets. The progressive growth of the hyper-connected world is pushing photonics to an inflection point. Now, it’s not if but when? Starting with cloud data centers, DCI-to-DCI, Metro and long-haul transport networks, and 5G basestations will enable the momentum and drive the demand for silicon photonics based solutions and deployments ports. As we approach 2017, we should see an inflection point for data center OEMs and telecom operators. Ultimately, all that demand for high speed, high bandwidth data in telecommunications and data centers will propel ecosystem growth and silicon photonics technologies.. To learn more about hypercloud data center solutions with breakthrough semiconductor technologies, download this recent presentation or contact your GLOBALFOUNDRIES sales representative.