By Dave Lammers

Now that magneto-resistive random access memory (MRAM) has reached the point — after more than two decades of development — where it can be more widely used, the question becomes: How will designers use it? How will MRAM make a difference in the connected systems in mobile, automotive, and IoT? MRAM pioneer Everspin Technologies (Chandler, Ariz.) has been shipping discrete MRAMs made by GF, largely to the cache buffering market, for the past two years, said analyst Tom Coughlin. With speeds rivaling DRAMs, and basically unlimited data retention, Coughlin said MRAM “is the best candidate for replacing existing non-volatile memories in computer architectures.”

Mobile devices and other systems often have large amounts of SRAM, Coughlin said, and must use time and energy to preserve the memory state when the power is turned off, or a system gets hung up. Because MRAM can be turned off and on with virtually no additional power consumption, system designers can do much more power cycling, turning power off to conserve battery life. There is no energy penalty when a normally-off system comes back to life. “For mobile devices, MRAM enables a lot more power-saving modes, which can help battery-powered systems,” Coughlin said. MRAM’s power-saving capabilities are somewhat surprising, because the early knock on MRAM was that it consumed a lot of power. Over the past 25 years the technology has gone from a thermally-assisted, sandwich-layer MRAM to a perpendicular magnetic tunnel junction, spin-transfer (pMTJ ST-MRAM) architecture. Back to the question: Where does MRAM fit? First, think about how fast the electronics industry is changing and where the opportunities are. New product categories such as augmented reality systems, assisted driving vehicles, drones, and a panoply of IoT technologies, are right in front of us. Dave Eggleston, the vice president of embedded memory at GLOBALFOUNDRIES, points out that most of these new systems depend on fast visual image processing. A car must process image data in real time to avoid a crash, requiring visual image processors and fast memories. “A drone is a great example of where you need lighter weight, and where more energy-efficient circuitry results in longer fly times. How does a drone navigate? By pulling in 3D maps. It has its own vision system, with stored information on topography, to hash real-time information,” Eggleston said. With MRAM, it is possible to trot out some impressive characteristics: 1000x more endurance and 1000x faster write speeds than eFlash; more dense and versatile than SRAM, and an ability to integrate into a CMOS logic process without disturbing the logic transistors. Also, embedded MRAM (eMRAM) is a low-mask-count technology, requiring only four additional mask layers compared with a dozen or more for eFlash at advanced nodes. Early on, Eggleston didn’t envision MRAM being immediately suitable to embedded applications. “I’m not sure I would have told you that ten years ago. But because the magnetic junctions are built in the back end of the line, and are easier to integrate in a logic process, the embedded applications make sense,” he said.

MRAM as Working Memory

To think of eMRAM as simply replacing something else probably is not the best way to think of it, especially in the advanced SoCs needed for emerging markets. It opens new possibilities in the working memories for mobile, IoT, automotive, and other connected applications, Eggleston said. For a complex chip with, say, four graphics processing units and a visual processing unit, an MRAM module could store the code and another block of eMRAM could store data. “By storing data in a non-volatile media, you don’t get rid of SRAM, because eMRAM does not run as fast, but you can shrink down the amount of SRAM and utilize eMRAM as an SRAM-like memory. That makes the design cost effective because eMRAM is denser than SRAM. You get more data for a smaller chip size,” Eggleston said. Software and SoC designers will learn new capabilities, taking advantage of the “persistence” (data retention) characteristics of eMRAM. The cost and performance benefits of eMRAM are what Eggleston calls the “table stakes” needed to make eMRAM a credible alternative to eFlash. But it will be the new capabilities brought by eMRAM that will entice system designers to ask ‘Now, how else can I use it in my chip architecture?’ Coughlin, who earlier worked in technology management at several disk drive companies, said MRAM “definitely has a niche replacing some DRAM and SRAM. It may replace NOR. What we are seeing is almost a Cambrian explosion in the memory field, where NAND flash will continue for mass storage while we see another tier of storage where MRAM or the Intel-Micron phase change memory is used in some applications.” As new applications call for higher performance, and as IoT systems generate much more data, systems designers will use multiple layers of memory. SRAM and DRAM will be complemented by new layers of phase change or resistive memories, and NAND, Coughlin said. “It will be a very interesting time, and we will see how it all shakes out. I do believe MRAM has a solid basis for being part of that menagerie,” he said.

22FDX® eMRAM

Eggleston said GF will continue to extend embedded flash, but GF’s plan is to marry eMRAM with another technology that has mask-count advantages: the 22FDX platform based on fully depleted SOI. The 22FDX-based products will begin to come to market in 2017, and Eggleston said eMRAM becomes available the following year. That timeline contrasts with a normal four or five years to bring NVM to a new logic technology. “For customers that need embedded memory, to bring eMRAM to 22FDX so soon after the (22FDX) logic launch is a huge win. With eMRAM, customers don’t need to recharacterize their designs, because the eMRAM is an extension of the platform, not a platform in and of itself,” he said. Since eMRAM does not shift the underlying transistors, designers can efficiently build a 22FDX-based SoC with the integrated eMRAM that runs on a logic voltage. “eMRAM is straightforward, it integrates incredibly well, and runs on a logic voltage,” he said.

Manufacturing Experience

Other companies have publicly referred to their own MRAM development programs. Coughlin noted that Everspin, which earlier took CMOS logic wafers and added its MRAM to the back end of the line, now works with GF as its full manufacturing partner. The 256-Mbit and, soon, 1 Gigabit-density discrete MRAMs sold by Everspin are made by GF. Coughlin estimates that about 60 million discrete MRAMs have been sold by Everspin thus far.

Source: Everspin, MRAM Leadership Over Three Generations

The years of manufacturing experience GF has gained by working with Everspin have provided key learning in deposition, etch, metrology, and other manufacturing processes that are unique to the multi-layer magnetic stacks within MRAMs. Coughlin said the manufacturing and technology partnership with Everspin has provided GF with a lead in the eMRAM arena. “I think it is a very important, pioneering effort. It has given the partners a lead in actual products, but they must be diligent to keep their lead,” Coughlin said. Eggleston said the spin-transfer MRAM work between GF and Everspin has provided “a lot of learning cycles” over the past two years of running wafers. “By the time we are in production with 22FDX eMRAM we will have been fabricating MRAM for four years. That definitely accelerates the time to market for our embedded solution,” he said.

GLOBALFOUNDRIES’ VP of the ASIC product line shares how the team’s rigorous approach to design implementation and methodology were critical factors in achieving first-time silicon success for a major networking customer. Designing complex ASICs and delivering them on time is no easy task. It requires a powerful combination of design expertise, proven methodologies, and robust process technology. One year ago, with the launch of GF’ first ASIC platform, FX-14®, we gained competitive ground with a new pipeline of ASIC offerings on our 14nm FinFET process technology (14LPP). Since then, we have combined a rich legacy of ASIC expertise from our acquisition of IBM Microelectronics with manufacturing scale and improved access to IP and design tools to enable a new generation of customers to easily adapt their chip designs to the FX-14 offering.

GF has decades of high-speed interconnect, memory, processor, and packaging innovation

Today, I am pleased to share an exciting milestone in our journey: We have achieved first-time-right silicon success for a lead product using our FX-14™ ASIC platform, with a major networking customer (to remain anonymous) bringing up a board in one week and declaring a fully functional ASIC chip. Such an aggressive schedule would be impressive for any product, but this is no ordinary chip—the highly complex design incorporated a high-performance ARM® 64-Bit core, a DDR memory subsystem including DDR memory controllers and PHYs, multiple high-speed backplane SerDes covering a broad range of interface standards, dense 1- and 2-port SRAMs, high-frequency I/Os, and PLLs. How did we accomplish this? A key factor in our approach is the use of an integrated test chip based methodology to rigorously vet our design implementation and methodology well in advance of customer product tapeout. Our ASIC design-for-test features include full scan, IEEE 1149.1 and 1149.6 JTAG boundary scans, and complex IP that meets the IEEE 1687 standard. Additionally, we use a three-phase netlist signoff process with stringent entrance and exit milestone requirements. This type of ASIC platform rigor before product tapeout is essential to enabling first-time customer success. Another key contributor was the maturity of the 14LPP manufacturing technology at our Fab 8 facility in upstate New York, which is in high-volume production on multiple products. By leveraging the FX-14 design platform, the team was able to turn around defect-free parts quickly in order to guarantee first-time-right silicon, while also achieving a power reduction of more than 50 percent over the customer’s previous design. Achieving first-time-right silicon success and fast board bringup for such a complex chip demonstrates the power of GF’ ASIC FX-14 design system. This, along with our proven expertise and design methodology, helps ensure that our customers can design with confidence and achieve a fast path to volume production. Today, we have many customer designs underway in FX-14 across a number of segments, including wired networking, wireless base station, compute, storage, and aerospace and defense applications. We are committed to partnering with these and other customers to help them bring their most complex designs to market.

By Sanjay Charagulla

Cloud computing and high-performance computing (HPC) are changing the data center industry in a big way. The biggest drivers in this space are consumerization and big data, putting our trajectory on steroids. Global cloud IP traffic will more than quadruple over the next 5 years, growing at a CAGR of 33 percent from 2014 to 2019, and accounting for more than 80 percent of total data center traffic. Also, more than 86 percent of workloads will be processed by cloud data centers. As the rapid pace of change continues, server computing and data storage requirements will continue to grow at a significant rate across the data centers, resulting in data center OEMs deploying more and more servers and storage.

Source: Cisco VNI Global Cloud Index, 2016

 

It was only a few years ago when companies were debating if they were ready for the cloud. Today, it’s no longer a question of if – it’s about how much they can get out of the cloud services. Server processor shipments are estimated to grow by an average rate of nearly 25 percent CAGR for the next four years, reaching a total of about 25 million processors. For example, out of 11+ million servers shipped last year, x86 chipsets were used in 9.8 million of them. In the second quarter of 2016, Intel accounted for 99.7 percent of x86 server-chip shipments. The cloud is also forcing changes to long established players in the hardware and software worlds. Recently, IBM unveiled new details of its Power9 chip —the next addition to the line of microprocessors the company plans to use in its own servers—and AMD announced its new Zen technology for server chips. Here is IBM’s official Power processor roadmap from last year, and see how AMD’s Zen microarchitecture is different from its other server cores. As data server companies seek to increase power and performance while reducing costs, chipmakers are up to the challenge to find ways to increase speed and functionality to devices while keeping costs low. For example, because of its competitive power and performance, with a ~10 percent lower die size, GLOBALFOUNDRIES’ advanced 14nm FinFET technology (14LPP), supports a wide range of products from mobile devices to servers, such as AMD and IBM’s server chip products. Enabled chip x86 processor performance by 3GHz+, the GF’s 14nm FinFET technology taps the benefits of three-dimensional, fully-depleted FinFET transistors, and offers impressive gains over 28nm bulk CMOS with up to 50 percent increase in performance and a 65 percent reduction in total power.

Source: GF Technology Conference 2016

The IBM and AMD announcements along with GF competitive advanced node technology, represent new competition to Intel’s dominance in the server market. In a recent strategy shift, IBM’s Power9 architecture will be offered to other hardware companies. Subsequently, IBM Power9 processors are not only targeting to HPC and enterprise server markets, but also enabling solutions for big data analytics, artificial intelligence, cognitive and hyper-cloud computing platforms. At a Silicon Valley technical conference this summer, AMD rolled out a demonstration of the performance with a head-to-head comparison of its Zen Core, claiming a 5x improvement in cache bandwidth with the redesigned memory subsystem. Overall, it is a core that contributes a 75 percent higher capacity to schedule instructions and a 50 percent greater ability to execute and issue them. With the advent of cloud computing, large service providers such as Google, Facebook, and Amazon are opting for systems based processors and open-source or in-house applications. Earlier this year, Google announced that they are working with Rackspace to co-develop an open server architecture design specification based on IBM’s new Power9 CPUs. The partnership with Nvidia should also help IBM’s Power9 become popular in servers as well as in supercomputers. Along with these two server giants, many other ARM processor-based chip vendors and other startups are building ARM server chips to target cloud datacenter markets. ARM estimates that 13 companies already are using its technology in chips for servers and other data-center hardware, which are expected to compete predominantly in single-socket and dual-socket servers with Intel server chip products. Server companies and other ARM based chip vendors are aiming at Intel’s chip dominance, targeting the~$12B server market for scale-out data centers. Overall in the next few years, these processor technologies and new solutions could begin driving a 15–25 percent growth in the server chip market.