GLOBALFOUNDRIES Announces Enhanced RF SOI Process Design Kit For Use with CWS’ SiPEX™ Design Solution September 18, 2017Enhanced PDK incorporates design productivity tool to further enhance high-performance RF SOI switches Santa Clara, Calif., September 18, 2017 — GLOBALFOUNDRIES today announced the availability of a new set of enhanced RF SOI process design kits (PDKs) to help designers improve their designs of RF switches and deliver differentiated RF front-end solutions for a wide range of markets including front-end modules for mobile devices, mmWave, 5G and other high-frequency applications. GF’s advanced RF technology platform, 7SW SOI, is optimized for multi-band RF switching in next-generation smartphones and poised to drive innovation in Internet of Things (IoT) applications. Designed for use with Coupling Wave Solutions’ (CWS) simulation tool, SiPEX™, GF’s 7SW SOI PDK allows designers to integrate RF switches with other critical RF blocks that are essential to the design of complex electronic systems for future RF communication chips. Specifically, this new capability allows designers to improve RF simulation output by simulating a highly-resistive substrate parasitic effect across their entire design. “GF leads the industry in RFSOI technology, and we are committed to providing our customers with design productivity solutions for our RF processes,” said Bami Bastani, senior vice president of RF at GF. “CWS’ SiPEX™ tool provides our customers with best-in-class correlation between simulated results and real world measurements, further optimizing the design layout to achieve efficiency and deliver differentiated RF front-end solutions.” “This is great news for the RF design community,” said Brieuc Turluche, chairman of the board of directors and chief executive officer of CWS. “The integration of SiPEX into GF’s RF SOI PDKs is a major milestone to achieve first-time correct complex and optimized RF SOI designs for high-performing cellular, IoT, 5G and Wi-Fi communication chips.” GF’s RF SOI technologies offer significant performance, integration and area advantages in front-end RF solutions for mobile devices and RF chips for high-frequency, high-bandwidth wireless infrastructure applications. CWS’ SiPEX accelerates the design of RF SOI switches by improving linearity simulation accuracy. It can also be effective in the design of low-noise amplifiers (LNA) and power amplifiers (PA), enabling designers to reduce their size to lower costs SiPEX™ is available in the current release of GF’s 7SW SOI PDK. For more information on the company’s RF SOI solutions, contact your GF sales representative or go to www.globalfoundries.com. About CWS CWS is the leader in system-level interference analysis of complex designs incorporating RF and analog blocks. Currently, CWS offers two products: WaveIntegrity™ and SiPEX™. Based on a unique harmonic analysis approach, WaveIntegrity™ is used by chip architects and designers to drive the chip design floorplanning. It is also used by package and PCB designers to integrate the noise-related design constraints in the final chip operational environment. SiPEX™, already included in TowerJazz’s CS18 and STM’s H9 SOI FEM Process Design Kits, improves the linearity of RF SOI designs and accurately models and simulates critical RF functions for 5G and IoT communications. Founded in 2005, CWS’ offices are located in Paris, Grenoble, France and San Jose, CA, USA. More information about the company, its products, and services is available at www.cwseda.com. About GF: GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. GLOBALFOUNDRIES is owned by Mubadala Investment Company. For more information, visit https://www.globalfoundries.com. Contacts: Erica McGillGLOBALFOUNDRIES(518) 305-5978[email protected]
网络应用的2.5D到来 August 30, 2017作者: Dave Lammers 面对带宽问题,网络公司正在转向转接板、HBM2 DRAM和先进ASIC技术。 当大网络公司开始开发新一级别的兆兆位路由器时，他们都来到了一个“临界点”，“临界点”概念是由The Linley Group的网络分析师Bob Wheeler提出的。 Cisco, Juniper, Nokia, 以及其他大公司在努力从层叠印制电路板DR DRAM中取得足够带宽的同时, 已经发现了针脚数目爆炸式的增长。 网络客户现已可使用由格芯提供的全新14纳米ASIC (FX-14™) 方案，此方案提供载于硅转接板上的高带宽内存(HBM2)链接。Rambus Inc. 公司(位于森尼维尔) 与格芯工程师合作，将 Rambus PHY 整合至 FX-14 ASIC 平台，提供了令人叹为观止的 每秒2 (Tb/s) 的带宽。 “外置内存无法跟上ASIC缓冲的带宽需求，这是已预见的问题，而这就是本问题的解决办法，” Wheeler 说道。 “人们尝试尽可能地使用通用型 DRAM，但是由于针脚数目的爆发式增长，现在我们正面临着一个临界点。” 通讯类ASIC的市场大概为十亿美元，Wheeler 提到, 而路由器是十分昂贵的系统，足以支持转接板 (2.5D) 方案满足高速数据缓冲的成本。 对于层叠PCB上的DDR型DRAM来说，Wheeler 声称 “ASIC的主要问题来自针脚数。设备的针脚数甚至可高达2000。HBM的魅力在于它具备通用的接口，并且包括在封装内一体化提供，无需寻求额外的接口。” 网络以外的市场? 取决于成本是否可以降低， 2.5D (转接板)方案可用于其他应用例如数据处理、高端图像、自动驾驶车辆、人工智能和其他高带宽类方案，格芯封装研发部、业务技术营运部副总裁 Dave McCann如此说道。 向转接板技术转移在排线密度上带来了巨大的进步。对于层叠PCB方案来说，连接线和线之间的空隙为12微米，可是由于垂直过孔50微米是不可取的，大量的空间被浪费在绕过或避免垂直过孔，通常连线密度无法达到理想值。有了硅转接板的帮助，连接线及空隙可达到逻辑芯片背板的级别，约为0.8微米，格芯技术开发高级经理Walter Kocon说道。 要在PHY和HBM2内存间使用逻辑级别的排线，需要依靠包括了光刻在内的晶元级工具。由于转接板比传统芯片更大，多处区域需被拼接在一起。但是 Kocon声称现下的分档器在刻线切换能力上非常出色，在创造更大转接板的道路上也取得了长足进展。 晶元长的工具比传统层叠制程工具要更昂贵，但是回报也同样巨大-芯片上的I/O可高达约1700个。正如McCann提到的，缩小单段排线的距离可将功耗保持在可控制范围，而这是目前仍在使用的层叠序列接口无法做到的。 全方位应用无死角 “由于晶元制造技术(小于1微米)在转接板中的应用,过孔技术得以实现,0.8微米排线和间隙可以在多个层面得到实现,而从根本上来说,并没有过孔无法应用的死角。对于传统PCB来说,排线必须从ASIC引入再回到DIMM卡上,浪费了能源与时间,”McCann说道。而基于转接板的内连接在数量级上更小，设备间的距离只有数百微米，大量的平行排线密度足以支持多兆兆位级别的带宽。 可是在转接板技术上存在制造难题。 “转接板和ASIC本身的尺寸很大。首先，我们必须创造ASIC和转接板之间的接口。拓展属性的匹配是创造合适接口的关键之一。控制扭曲的设计和集成处理尤为重要。将压力均匀散布于转接板和位于其下的叠层也十分重要，否则接口将存在巨大误差。” McCann 说道。 转接板和ASIC之间十分靠近，而焊锡凸块大约为70微米，在这个前提下，控制扭曲是增加2.5D技术产量的关键因素。 “这意味着产品对于扭曲的容忍性将极为有限，” McCann 说道。被推向一起的焊锡或被向反方向拉扯的焊锡将带来链接上的问题。 “我们要求制造加工保证所有分层都为平面，但我们相信在OSAT合作伙伴的帮助下，我们可以满足这个要求。” McCann 说道。 PHY合作 PHY是另一个技术难题，这个难题已被 Rambus和格芯一同克服。 Frank Ferro是Rambus产品市场部高级主管，他解释说，HBM2 PHY是一个混合信号功能，必须针对每个制程节点进行精确设计。 “我们进行了大量的信道建模，并设计了满足各种要求的PHY。而这些都是通过合作开发完成的。我们对于整个制程进行了许多讨论，以确保设计的稳定。项目伊始，让设计成功实现，就是Rambus的（建模和信号完整性）工具和参与到设计这些PHY的所有工程师的目标。” DDR DRAM支持72数位的带宽，而HBM2支持1024位。1024数位的信号完整性控制极具挑战性，Ferro向格芯工程师们寻求帮助，指望于他们从IBM微电子部门带来的高速信号经验。 当被问及2.5D方案是否将占领整个行业的高速部分，Ferro称这将取决于制造的产量以及HBM2 DRAM的成本减少。 “2.5D 必须经由大批量制造的考验。这是硅技术中极大的一部分，扭曲必须得到控制。” Tad Wilder是格芯技术员工的高级成员, 他声称2兆兆位每秒的带宽“对于单一核心来说是令人叹为观止的。而总共可放置4块HBM2 PHY的芯片，将为ASIC设计者带来前所未有的8兆兆位每秒的带宽，并具备低功耗低延迟DRAM。”他补充道14纳米 HBM PHY “是我们为ASIC生产过最大的核心，其包含15000外置针脚可接至内存控制器、1700外置针脚可接至转接板各层DRAM的基本晶体。” 每一层DRAM都包含一个基础晶体，与ASIC的HBM2 PHY以及另外高达8个不同叠层的基础晶体进行沟通，链接通过数千个垂直硅过孔（TSV）实现。每层HBM DRAM的总内存可高达32GB。为了减少1000个输入输出开关的噪音信号，ASIC HBM2 PHY可以利用8个128数位信号通道的完全独立性，并通过对每个信号通道的相应时序控制调整来实现。 Linley Group分析师 Wheeler见证了HBM2标准建立所带来的趋势。Hynix是最初的发起者，可是 Wheeler说 Samsung已具备自己的HBM2并愈发强势。由于方案的成本大部分来自于HBM2内存，多个HBM2供应商间将展开激烈竞争，提高产量、降低成本并优化性能。 当被问及是否认为2.5D方案将进一步普及，McCann说 “这是本时代一个非常伟大的技术，并能带来巨大的回报。问题是，我们是否能降低成本并提高产量？” 关于作者 Dave Lammers是固态技术特约撰稿人，也是格芯的Foundry Files的特约博客作者。他于20世界80年代早期在美联社东京分社工作期间开始撰写关于半导体行业的文章，彼时该行业正经历快速发展。他于1985年加入E.E. Times，定居东京，在之后的14年内，足迹遍及日本、韩国和台湾。1998年，Dave与他的妻子Mieko以及4个孩子移居奥斯丁，为E.E Times开设德克萨斯办事处。Dave毕业于美国圣母大学，获得密苏里大学新闻学院新闻学硕士学位。
2.5D Arrives for Networking Applications August 22, 2017By: Dave Lammers Faced with bandwidth issues, networking companies are turning to interposers, HBM2 DRAM and leading-edge ASIC technology. When the big networking companies began developing a new class of terabit routers, they reached what Bob Wheeler, networking analyst at The Linley Group, calls “the breaking point.” These companies — Cisco, Juniper, Nokia, and others — had been watching the pin counts on their router ASICs “explode” as they worked to get enough bandwidth from commodity DDR DRAMs, mounted on laminate printed circuit boards. Networking customers are now able to use a new 14nm ASIC (FX-14™) solution from GLOBALFOUNDRIES® which offers connections to High-Bandwidth Memory (HBM2) mounted on a silicon interposer. Rambus Inc. (Sunnyvale) and GF engineers cooperated to bring a Rambus PHY to the FX-14 ASIC platform that provides an impressive 2 terabits per second (Tb/s) of bandwidth. “This is a solution to a problem we’ve seen coming, which is the inability of external memory to keep up with the bandwidth requirements on the buffers of these ASICs,” Wheeler said. “People tried to use commodity DRAM as long as they could, but because of the pin count explosion, that reached a breaking point.” The market for communications ASICs is roughly a billion dollars, Wheeler said, noting that routers are expensive systems that can support the cost of an interposer-based (2.5D) solution to get the bandwidth required for high-speed packet buffering. For the incumbent — DDR-type DRAM running on a laminate PCB — Wheeler said “the big problem from the ASIC perspective was the pin count. You could end up with 2,000-plus-pin devices. The beauty of HBM is that it has a wide interface and stays in the package, so you don’t have to go to a serial interface.” Markets Beyond Networking? Depending how well costs can be improved, the 2.5D (interposer-based) solutions could find other applications in data processing, high-end graphics, self-driving cars, artificial intelligence, and other bandwidth-hungry solutions, said Dave McCann, vice president of packaging R&D and business technical operations at GLOBALFOUNDRIES. Moving to an interposer brings an enormous improvement in the routing density. For laminate PCB-based solutions, lines and spaces were at 12 microns, but that wiring density often was not achieved because the vertical 50-micron vias between the layers had to be avoided, or routed around, wasting a huge amount of space. With a silicon interposer, the lines and spaces are essentially the same as the back-end of a logic chip, currently about 0.8 microns, said Walter Kocon, a senior manager of technology development at GF. Using logic-like wiring for routing between the PHY and the HBM2 memory on an interposer involves using fab-level tools, including lithography. Because the interposers are much larger than conventional chips, multiple fields must be stitched together. But Kocon said today’s steppers are very good at switching between reticles, and progress is being made in creating ever-larger interposers. These fab processing tools are more expensive than conventional laminate-processing tools, but the payback is a massive number of on-chip I/Os (roughly 1,700) between the PHY and the HBM2 memory. And as McCann noted, by keeping the traces very short, power consumption is kept under control compared with the laminate-based serial interfaces used to date. No Keep Out Area “With vias enabled by wafer fab technology (<1 micron) in silicon interposers, multiple layers of 0.8-micron lines and spaces can be utilized, because there is essentially no keep out area for the vias. That compares with the conventional PCBs, where routing had to come down from the ASIC and over to the DIMM card, consuming both power and time,” McCann said. With interposer-based interconnect being orders of magnitude smaller, and devices only hundreds of microns apart, the massively parallel routing density supports multi-terabit levels of bandwidth. But there are manufacturing challenges associated with interposers. “These are big interposers and big ASICs. First, we have to create an interface between the ASIC and the interposer. Matched expansion properties of the ASIC and silicon interposer are one key to a non-stressed interface. Design and assembly processes that control warpage are critical. Then spreading the stress between the interposer and the laminate below is critical, because there is a big mismatch at that interface,” McCann said. Controlling warpage is key to getting good interconnect yields with 2.5D. With very close spacing between the interposer and the ASIC and a bump height of about 70 microns. “This means there is very little tolerance for warpage,” McCann said. Solder that is pushed together, or pulled in the opposite direction, creates connection issues. “We need manufacturing processes to keep all of these surfaces flat, and we believe, along with our OSAT partners, that we can do that,” McCann said. PHY Cooperation The PHY was another technical challenge, one that Rambus tackled along with GF. Frank Ferro, senior director of product marketing at Rambus, explained that an HBM2 PHY is a mixed signal function that must be designed very specifically to each process node. “We do a significant of amount channel modeling and then designed the PHY to meet those channel requirements. And it was a collaboration. We had many discussions over the whole process to ensure a robust design. From Day One, it worked, and that is a strong testament to the Rambus (modeling and signal integrity) tools and the engineers who have a history of designing these PHYs.” DDR DRAMs support 72 bits of bandwidth, compared with 1,024 for HBM2. With 1,024 bits, controlling the signal integrity is challenging, and Ferro tipped his cap to the GF engineers, many of whom brought experience with high-speed signaling from their days at IBM’s Microelectronics Group. Asked if he thought 2.5D solutions would spread throughout the high-performance part of the industry, Ferro said it depends on manufacturing yields, and bringing down the cost of the HBM2 DRAM. “2.5D needs to be proven out with high-volume manufacturing. It is a fairly big piece of silicon, and you have to really control warpage.” Tad Wilder, a principal member of the technical staff at GF, said the 2 terabits-per-second of bandwidth “is quite an impressive amount of bandwidth for a single core. And with the ability to place up to four HBM2 PHYs on a chip, this gives ASIC designers an unprecedented eight terabits-per-second of low power, low latency DRAM access to work with.” He added that the 14nm HBM PHY “Is the largest core we’ve produced for an ASIC, with 15,000 internal pins talking to the Memory Controller and 1,700 external pins talking to the base die of the DRAM stack across the interposer.” Each DRAM stack contains a base die, which communicates with the ASIC’s HBM2 PHY and up to eight stacked DRAM die above, through thousands of vertical Through Silicon Vias (TSVs). The total memory per HBM DRAM stack is up to 32GB. To mitigate the noise of more than 1,000 I/O possibly switching, the ASIC HBM2 PHY can take advantage of the complete independence of the eight 128 bit channels by skewing the timing of each channel with respect to another. Linley Group analyst Wheeler sees momentum building for the HBM2 standard. While Hynix was the initial backer, Wheeler said Samsung has come on strong with its own HBM2 parts. Because so much of the total solution cost is wrapped up in the cost of the HBM2 memories, competition among multiple HBM2 vendors will help drive volumes, reduce costs and improve performance. Asked if he thought 2.5D solutions would proliferate, McCann said “it is a really great technology that has come of age, with significant revenues. The question is: can we drive down the cost to get it to the next level of volume?” About Author Dave Lammers Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.
格芯展示应用于数据中心、网络和云应用的2.5D高带宽内存设计方案 August 10, 2017本方案利用2.5D封装技术,低延迟、高带宽内存PHY，使用FX-14™ ASIC设计系统搭建 加州圣克拉拉，2017年，8月9日- 格芯在今天公布，已为ASIC的14纳米高性能FinFET FX-14™集成设计平台展示了2.5D封装方案。 2.5D ASIC方案与Rambus，Inc.协作开发,包括了一个内置的插入转接板设计以克服光刻局限，也包括了每秒2T的多通道HBM2 PHY. 本方案在14纳米FinFET技术平台搭建,将集成于在7纳米 FinFET制程技术打造的下一世FX-7™ ASIC设计系统。 “由于近年来内连接和封装技术的巨大进步，制程与封装之间的分界线愈发模糊，”格芯ASIC产品发展部副总裁Kevin O’Buckley说道。“将2.5D封装应用于ASIC设计以增强性能是能力的自然进化。这让我们得以为客户提供一站式端到端的技术支持：从产品设计一直到生产和测试。” Rambus的内存PHY目标在于高端网络和数据中心应用，提供对数据要求最高的任务，满足低延迟和高带宽的系统要求。PHY技术与JEDEC JESD235 HBM2标准吻合，每个数据接口可支持高达2G的数据传输率，总带宽可达2Tbps。 “我们努力提供完善的HBM PHY技术，帮助数据中心和网络连接方案供应商达成如今最高要求的工作量，并把握住市场机会，”Rambus内存和接口分部高级副总裁、总经理Luc Seraphin说道。“我们与格芯合作，结合了我们的HBM2 PHY和格芯的2.5D封装、FX-14ASIC 设计系统，为业内告诉增长的应用提供了高度集成的设计方案。” FX-14和FX-7是完整的ASIC设计方案，利用了格芯使用FinFET制程大批量生产的经验，包含了业内应用最广泛、最具备深度的IP组合，提供了为下一代连线/5G无线网络连接、云/数据中心服务器、机器学习或深度学习、汽车和航空航天或国家防御应用的独特方案。格芯是世界上唯一两家提供最优IP和高级内存及封装方案的公司之一。 关于格芯： 格芯是提供设计开发和制造间独特组合的领先全方面服务代工厂，为全世界的先进技术公司提供服务。格芯铸造厂遍布全球三大洲，提供了改造行业的能力，为客户带来重塑市场的能力。格芯隶属Mubadala发展公司。了解更多详情，请登录网址https://www.globalfoundries.com 联系方式: Erica McGill GLOBALFOUNDRIES (518) 795-4250 [email protected]
GLOBALFOUNDRIES Demonstrates 2.5D High-Bandwidth Memory Solution for Data Center, Networking, and Cloud Applications August 10, 2017Solution leverages 2.5D packaging with low-latency, high-bandwidth memory PHY built on FX-14™ ASIC design system Santa Clara, Calif., August 9, 2017 – GLOBALFOUNDRIES today announced that it has demonstrated silicon functionality of a 2.5D packaging solution for its high-performance 14nm FinFET FX-14™ integrated design system for application-specific integrated circuits (ASICs). The 2.5D ASIC solution includes a stitched interposer capability to overcome lithography limitations and a two terabits per second (2Tbps) multi-lane HBM2 PHY, developed in partnership with Rambus, Inc. Building on the 14nm FinFET demonstration, the solution will be integrated on the company’s next-generation FX-7™ ASIC design system built on GF’s 7nm FinFET process technology. “With the tremendous advances in interconnect and packaging technology that has occurred in recent years, the line between wafer processing and packaging has blurred,” said Kevin O’Buckley, vice president of ASIC product development at GF. “Incorporating 2.5D packaging into ASIC design boosts performance beyond scaling and is a natural evolution of our capabilities. It enables us to support our customers in a one-stop end-to-end fashion, from product design all the way through manufacturing and testing.” The Rambus memory PHY is aimed at high-end networking and data center applications performing the most data-intensive tasks in systems requiring low-latency and high-bandwidth. The PHY is compliant with the JEDEC JESD235 HBM2 standard, supporting data rates up to 2Gbps per data pin, enabling a total bandwidth of 2Tbps. “We strive to deliver comprehensive HBM PHY technologies that will enable data center and networking solution providers to meet today’s most demanding workloads and take advantage of compelling market opportunities,” said Luc Seraphin, senior vice president and general manager, Memory and Interfaces Division at Rambus. “Our collaboration with GF combines our HBM2 PHY with their 2.5D packaging and FX-14 ASIC design system and provides a fully-integrated solution for the industry’s fastest-growing applications.” FX-14 and FX-7 are complete ASIC design solutions that take advantage of GF’s experience in volume production with FinFET process technology. They comprise functional modules based on the industry’s broadest and deepest intellectual property (IP) portfolio, which makes possible unique solutions for next-generation wired/5G wireless networking, cloud/data center servers, machine learning/deep neural networks, automotive, and aerospace/defense applications. GF is one of only two companies in the world that delivers best-in-class IP plus advanced memory and packaging solutions. About GF: GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. GLOBALFOUNDRIES is owned by Mubadala Development Company. For more information, visit https://www.globalfoundries.com. Contact: Erica McGillGLOBALFOUNDRIES(518) 795-4250[email protected]
格芯携手Silicon Mobility,打造业内首款汽车FPCU, 进一步推进混合动力与电动力车辆性能 August 3, 2017Silicon Mobility通过格芯的 55nm LPx平台, 配备 SST高可靠性 SuperFlash®内存技术, 增强了汽车性能、能源效率与安全等级 加州圣克拉拉，2017年8月3日 – 格芯与Silicon Mobility在今天宣布已成功制造出业内第一款汽车可编程场控制器单元 (FPCU)设计方案, 并将其命名为 OLEA® T222。FPCU 使用了格芯的55nm低功耗拓展 (55LPx) 技术平台, 此平台通过了汽车等级验证, 包括了硅存储技术 (SST) SuperFlash® 内存技术, 在单芯片内集成了多个功能, 增强了混合动力和电动力车的性能。 Silicon Mobility 的 OLEA® T222让汽车自动化处理能力更加强力，通过在控制处理器结构中嵌入灵活逻辑单元 (FLU), 带来了高达40倍的处理加速和更好的实时控制能力。通过FLU的加速能力， OLEA® T222 提高了节能控制的质量，劲儿提高了安全性，并且在超快安全应用上满足了ASIL-D级标准。此外，汽车制造商可以增强DC/DC 和AC/DC控制的能源效率, 提高电池使用范围, 耐用性和电动机的充电速度。 “电动机、功率转换器和电池充电器的效率是混合和电动力汽车控制系统的关键因素,” Silicon Mobility 运营部副部长Vincent Cruvellier说道。 “格芯的 55LPx 平台配备了快速和低功耗的逻辑和汽车1级认证，结合了SST的高可靠性 SuperFlash 内存技术，让我们可以在一块芯片上集成多种功能，打造出OLEA® T222 产品。格芯是全球性的专业汽车类市场代工厂，我们与格芯的合作使客户确保获得最高的产品质量、最高的可靠性和对于制造汽车类产品的支持。” 格芯的 55nm LPx可用于射频，经汽车等级验证的平台提供了通向生产的快速方案，其中包括了硅验证的射频IP以及SST的高度可靠SuperFlash内存，主要特点有： · 超快读取速度(<10ns) · 比特单元小尺寸 · 超强数据维持能力 (> 20 years) · 超强耐久力 (> 200K cycles) · 完全通过汽车1级认证 (AEC-Q100) “我们的平台结合了 Silicon Mobility的设计，提供55nm的高度集成的汽车自动化设计, 推出了业内第一款FPCU,” 格芯嵌入式内存部副部长 David Eggleston说道， “这是格芯55LPx平台受到广大市场欢迎的又一例证，特别是对于汽车应用这种对可靠性要求极高的市场。” 格芯的55LPx eFlash 平台正在新加坡300mm产品线进行批量生产。无论是对于穿戴式设备还是汽车的微控制器单元,55LPx eFlash平台是大量产品的最高成本效率方案。 设计工具包现已可用。用户已可使用该工具包对芯片设计进行优化，开发独特的SuperFlash方案，满足成本性能要求，低功耗和极限环境中的高可靠性。 了解更多关于格芯主流CMOS设计方案的信息，请与格芯销售代表联系或登录网址www.globalfoundries.com 关于Silicon Mobility: Silicon Mobility是更环保、更安全更智能移动应用的技术领先者。该公司设计开发并销售灵活、实时、安全而开房的半导体方案，供应追求能源效率、减少污染排放、保证乘客安全的汽车行业。 Silicon Mobility的产品控制电动机、电池和能源管理系统，应用于混合动力和电动力车辆。使用Silicon Mobility 的技术，制造商可以提高效率，减小尺寸、重量和电动机的成本，增加电池的使用范围和耐用性。Silicon Mobility的技术和产品加速了汽车动力系统的电子化，也推动了OEM无人车的开发。Silicon Mobility总部位于法国索菲亚科技园。了解更多详情请登录www.silicon-mobility.com 关于格芯 格芯是提供设计开发和制造间独特组合的领先全方面服务代工厂，为全世界的先进技术公司提供服务。格芯铸造厂遍布全球三大洲，提供了改造行业的能力，为客户带来重塑市场的能力。格芯隶属Mubadala发展公司。了解更多详情，请登录网址https://www.globalfoundries.com 联系方式: Erica McGill 格芯 (518) 795-5240 [email protected] David Fresneau Silicon Mobility +33 (0)487 791 020 [email protected]
GLOBALFOUNDRIES, Silicon Mobility Deliver the Industry’s First Automotive FPCU to Boost Performance for Hybrid and Electric Vehicles August 3, 2017Silicon Mobility and GF’s 55nm LPx -enabled platform, with SST’s highly-reliable SuperFlash® memory technology, boosts automotive performance, energy efficiency, and safety levels Santa Clara, Calif., August 3, 2017 – GLOBALFOUNDRIES and Silicon Mobility today announced they have successfully produced the industry’s first automotive Field Programmable Controller Unit (FPCU) solution, called OLEA® T222. The FPCU solution uses GF’s 55nm Low Power Extended (55LPx) automotive qualified technology platform, which includes Silicon Storage Technology’s (SST) SuperFlash® memory technology, to integrate multiple functions onto a single chip, boosting performance for hybrid and electric vehicles. Silicon Mobility’s OLEA® T222 allows automotive processing to be fully deterministic through embedding a Flexible Logic Unit (FLU), with up-to 40 times acceleration, into the control processor architecture to accelerate the processing and control of real-time events. With FLU acceleration, OLEA® T222 increases the quality of energy conversion controls to increase safety and achieve ASIL-D for ultra-fast safety applications. Moreover, automotive manufacturers can enhance energy efficiency of DC/DC and AC/DC controls as well as increase battery range, durability, and charging speed for electric motors. “Efficiency of electric motors, power converters, and battery chargers are key factors for hybrid and electric vehicle control systems,” said Vincent Cruvellier, vice president of operation at Silicon Mobility. “GF’s 55LPx platform, with its fast, low-power logic and Automotive Grade 1 qualification, combined with SST’s highly-reliable SuperFlash memory technology, allowed us to integrate multiple functions into a single chip, creating the OLEA® T222 product. Our collaboration with GF, a global foundry committed to the automotive market, helps ensure our customers have the highest quality, reliability and support for the manufacturing of our automotive products.” GF’s 55nm LPx RF-enabled, automotive-qualified platform provides a fast path-to-product solution that includes silicon qualified RF IP, SST’s highly-reliable SuperFlash memory technology that features: Very fast read speed (<10ns) Small bitcell size Superior data retention (> 20 years) Superior endurance (> 200K cycles) Fully qualification for Auto Grade 1 operation (AEC-Q100) “Our platform combined with Silicon Mobility’s design has delivered a highly integrated automotive solution at 55nm, achieving the first FPCU in the industry,” said David Eggleston, vice president of embedded memory at GF. “This is yet another example that GF’s 55LPx platform is becoming the preferred choice for a broad spectrum of markets, including automotive applications that require superior reliability in extreme environments.” GF’s 55LPx eFlash platform is in volume production at the foundry’s 300mm line in Singapore. The 55LPx eFlash platform is a cost effective solution for a broad range of products, ranging from wearable devices to automotive MCU’s. Process design kits are available now. Customers can start optimizing their chip designs to develop differentiated SuperFlash-enabled solutions that require cost effective performance, low power consumption, and superior reliability in extreme environments. For more information on GF’s mainstream CMOS solutions, contact your GF sales representative or go to www.globalfoundries.com. About Silicon Mobility: Silicon Mobility is a technology leader for cleaner, safer and smarter mobility. The company designs, develops and sells flexible, real-time, safe and open semiconductor solutions for the automotive industry used to increase energy efficiency and reduce pollutant emissions while keeping passengers safe. Silicon Mobility’s products control electric motors, battery and energy management systems of hybrid and electric vehicles. By using Silicon Mobility’s technologies, manufacturers improve the efficiency, reduce the size, weight and cost of electric motors and increase the battery range and durability. Silicon Mobility technologies and products accelerate the car’s powertrain electrification and the deployment of driverless vehicles for OEMs. Silicon Mobility is headquartered in Sophia-Antipolis, France. For more information, visit: www.silicon-mobility.com About GF GF is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GF makes possible the technologies and systems that transform industries and give customers the power to shape their markets. GF is owned by Mubadala Development Company. For more information, visit https://www.globalfoundries.com. Contact: Erica McGillGLOBALFOUNDRIES(518) 795-5240[email protected] David FresneauSilicon Mobility+33 (0)487 791 020[email protected]
Semiconductors On the Cusp of a Golden Era August 1, 2017By: Gary Dagastine Since the invention of the transistor, breathtaking advances in semiconductor technology have driven the evolution of computing and communications along a path from centralized mainframes and minicomputers, to networked PCs, to sophisticated mobile devices that can connect to networks at any time from anywhere. Yet as impressive as these achievements have been, they represent only the beginning of the contributions semiconductors will make to society. Their real impact is yet to come because while there are already billions of internet-connected devices in the world, a much greater number will be connected globally in the next few years for applications such as autonomous vehicles, the Internet of Things (IoT) and many others. They will require an extensive infrastructure to connect, transmit, process, act upon and store all of the resulting data. Building an infrastructure that can enable such “connected intelligence” is a huge ongoing task that will require so many semiconductors relying on so many technologies, that it’s fair to say a golden era is dawning for the industry. That was the perspective given recently by GLOBALFOUNDRIES CEO Sanjay Jha and Sr. Vice President and General Manager of Fab 8 Tom Caulfield, in keynote talks at the Mobile World Congress Shanghai and SEMICON West trade shows, respectively. Their talks were focused on describing this new era of connected intelligence, how it is changing the requirements and conditions for success in the foundry segment, and how GF is making it possible. Jha spoke about how the explosion of data is leading to a connected intelligence inter-relationship among data centers, networks and client devices (i.e., smartphones, IoT devices, etc.). He described how GF is in a leadership position to enable it, both with regard to GF’s suite of leading-edge technologies and in terms of the company’s business strategies, such as the building of a new 300mm fab in Chengdu, China for 22FDX®-based products. “The last 10 years in this industry have probably been the most transformative in our lives,” he said. “One example is that our phones have become an extension of our minds. Another, from a social perspective, is that Facebook now has almost 2 billion monthly users. Considering that China has about 1.4 billion people, the Facebook community is now larger than any other.” At MWC Shanghai, CEO Sanjay Jha was a keynote speaker and part of a panel speaking on the topic of “Industry & The Human Element” “I believe the next 10 years is going to be a golden era for the foundry business,” he said. “Industry estimates suggest that by 2025 we will be using 163 zettabytes of data (one zettabyte = 250 billion DVDs). We are collecting, transporting and analyzing all of this information – both at the edge with client devices for real-time decision-making and in the data center for longer-term insight gathering. Semiconductors are the enabling technology.” Jha believes this transformation is changing the conditions for success in the semiconductor industry – both in terms of technologies and customer engagement models. Regarding technologies, he described how GF’s dual roadmap of FDX™ technology for battery-powered devices and FinFET technology for high-performance processing in data centers and high-end computing devices is unique, and allows the company to match the right technology with the right application. When coupled with the company’s legacy of leadership in RF, its new silicon photonics technologies for connectivity, and differentiated ASIC and analog/power technologies, GF is in a unique position to drive progress across the full breadth of new applications in the years ahead. Regarding engagement models, Jha used China as an example, saying that, “The country is moving from a ‘Made in China’ stage of industry to an ‘Innovated in China’ position, and our Chengdu fab is a strategic, long-term joint venture partnership with the Chengdu government that is conceived in that light. It will be central to our IoT and 5G technologies, and when complete it will be the largest fab in China, with a building half a kilometer long.” Click here to view Sanjay Jha’s presentation. At SEMICON West, Caulfield said that ever since Gordon Moore’s famous observations known as Moore’s Law were made some 50 years ago, the industry has been putting the pieces into place for what comes next, in effect. “We’ve made products that are smart, and that’s great, but now we’re going to take ‘smart’ and do something special with it. We are moving beyond an internet of smart things, to a framework of ‘connected intelligence’ whose operation and capabilities in many ways mimic the way the mind works.” Tom Caulfield, SVP & GM of Fab 8, was a keynote speaker and a part of the opening ceremony for SEMICON West 2017 Caulfield noted that the engine powering this move is semiconductor innovation but that in order to keep achieving the technological progress predicted by Moore’s Law, the industry must operate differently because things have become so complex and inter-twined. Scaling is still critical, but scaling alone is no longer an effective strategy. “After 50 years the game is still ahead of us. We must redefine innovation, collaborate differently and shift engagement behaviors in order to drive needed innovation in data analysis, bandwidth, storage density and power management,” he said. He pointed to GF’s dual-technology roadmap as an example of how innovation is being redefined, with FinFETs representing one path forward for high-performance computing and FDX representing another path forward for wireless, battery-powered devices. With regard to collaborating differently, Caulfield noted that as the world has developed and the industry has grown and become more complex, old ways of doing business are no longer adequate. He said that a strategy of collaboration today needs to be built on three elements: strategic partnerships with key suppliers; “coopetition” with industry rivals, meaning to cooperate with them in some areas and compete with them in others; and public-private partnerships. He used the Albany Nanotech research facility as an example of the benefits of coopetition, saying, ”For the industry, it offsets our collective expense to develop technology at the leading edge and lets us build scale in key technologies on a virtual basis.” With regard to engagement behaviors, he said, “The industry is now so complex that we’ve reached the point where when you look at a project team it’s difficult to know who is the vendor and who is the customer. Sure, everyone has a boss, but they are really dedicated to the project.” That’s just one example of how engagement behavior needs to evolve, Caulfield said. “Sharing ideas across global teams, working in an interdisciplinary fashion and encouraging a diversity of ideas are absolutely vital to technical innovation in today’s world,” he said. Click here to view Tom Caulfield’s presentation. About Author Gary Dagastine Gary Dagastine is a writer who has covered the semiconductor industry for EE Times, Electronics Weekly and many specialized media outlets. He is a contributing editor at Nanochip Fab Solutions magazine and also is the Director of Media Relations for the IEEE International Electron Devices Meeting (IEDM), the world’s most influential technology conference for semiconductors. He started in the industry at General Electric Co. where he provided communications support to GE’s power, analog and custom IC businesses. Gary is a graduate of Union College in Schenectady, New York,
格芯与芯原联袂实现适合次世代物联网的单芯片解决方案 July 13, 2017采用格芯的22FDX® 技术的集成解决方案将减少NB-IoT及LTE-M应用的功耗、面积及成本 美国加利福尼亚圣克拉拉，及中国上海（2017年7月13日）——今日，格芯（GLOBALFOUNDRIES，原名格罗方德）与芯原微电子（VeriSilicon）共同宣布，将携手为下一代低功耗广域网（LPWA）推出业界首款单芯片物联网解决方案。双方计划采用格芯的22FDX® FD-SOI 技术开发可支持完整蜂巢式调制解调器模块的单芯片专利，包括集成基带、电源管理、射频以及结合窄带物联网（NB-IoT）与LTE-M 功能的前端模块。相较于现有产品，该全新方案可望大幅改善功耗、面积及成本。 随着智慧城市、家居与工业应用中互联设备的数量日益增加，网络供应商也着手开发全新的通讯协议，以期更加符合新兴物联网标准的需求。LPWA 技术利用现有的LTE频谱及移动通信基础设施，但更着重于为例如联网水表和煤气表等传输少量低频数据的设备提供超低功耗、扩大传输范围以及降低数据传输率。 两大领先的LPWA连接标准包括在美国前景看好的LTE-M，以及逐渐在欧洲、亚洲取得一席之地的NB-IoT。举例而言，中国政府已将NB-IoT定为明年全国部署的对象。根据美国市场研究公司 ABI Research 的研究，该两大技术的结合将推动蜂窝M2M模块的出货量到2021年可能逼近5亿。 格芯与芯原微电子目前已着手开发IP套件，以双模运营商等级的基调制解调器带搭配集成的射频前端模组，旨在让客户开发出成本及功耗优化的单芯片解决方案，以供全球部署。该款设计将采用格芯的22FDX工艺，运用22nm FD-SOI技术平台为物联网应用提供成本优化的微缩能力并降低功耗。22FDX是唯一能够以单芯片高效整合射频、收发器、基带、处理器和电源管理元件的技术。相较于现有的40nm技术，这款集成方案预计在功耗和裸片尺寸方面，将达到80%以上的提升。 格芯产品管理高级副总裁Alain Mutricy表示：“低功耗、电池供电的物联网设备正处于爆发性增长态势，22FDX技术完美契合了其需求。对中国市场带来的机会，我们尤为兴奋。中国正以领先姿态在全国范围大力发展物联网与智慧城市。芯原微电子是我们重要的合作伙伴，他们协助我们在成都建设以全新300mm晶圆厂为中心的FD-SOI生态系统。此次新的合作计划也将进一步深化我们的长期合作关系。” 芯原股份有限公司创始人、董事长兼总裁戴伟民表示：“自五年前开始，作为芯片平台即服务 (SiPaaS) 的设计代工公司，芯原即开始开发 FD-SOIIP，并基于FD-SOI 技术一次流片成功了多款芯片产品。就物联网应用而言，除了成本优势之外，集成式射频、体偏压以及嵌入式内存如MRAM，都是28mm CMOS 工艺节点往后，FD-SOI 技术所具备的重要优势。在格芯22FDX上集成射频与功率放大器后，基带和协议栈可在高能效且可编程的ZSPnano 上得以实现，ZSPnano 专为控制和具有低延迟的数据流、单周期指令的信号处理而优化。格芯位于成都的全新FDX 300 mm 晶圆厂，以及此次合作推出的集成式 NB-IoT、LTE-M单芯片解决方案等 IP 平台，都将对中国的物联网和 AIoT(物联人工智能) 产业带来重大的影响。” 格芯与芯原微电子预计将于2017年第四季度对基于此集成方案的测试芯片进行流片，并完成验证。双方计划于2018年年中获得运营商许可。 关于格芯 格芯是全球领先的全方位服务半导体代工厂，为世界上最富有灵感的科技公司提供独一无二的设计、开发和制造服务。伴随着全球生产基地横跨三大洲的发展步伐，格芯促生了改变行业的技术和系统出现，并赋予了客户塑造市场的力量。格芯由阿布扎比穆巴达拉发展公司（Mubadala Development Company）所有。欲了解更多信息，请访问 https://www.globalfoundries.com/cn。 关于芯原微电子 芯原股份有限公司（芯原）是一家芯片设计平台即服务（Silicon Platform as a Service，SiPaaS®）提供商，为包含移动互联设备、数据中心、物联网(IoT)、汽车、工业和医疗设备在内的广泛终端市场提供全面的系统级芯片(SoC)和系统级封装(SiP)解决方案。芯原的机器学习和人工智能技术已经全面布局智慧设备的未来发展。基于SiPaaS服务理念，芯原助力客户在设计和研发阶段领先一步，从而专注于差异化等核心竞争优势。芯原一站式端到端的解决方案则能够在短时间内打造出从定义到测试封装完成的半导体产品。宽泛灵活的SiPaaS解决方案为包含新兴和成熟半导体厂商、原始设备制造商（OEMs）、原始设计制造商 （ODMs），以及大型互联网和云平台提供商在内的各种客户提供高效经济的半导体产品替代解决方案。芯原的从摄像头输入到显示/视频输出的像素处理平台由高保真 ISP，支持机器学习加速的嵌入式视觉图像处理器（VIP），Vivante®低功耗GPU和高性能GPGPU，Hantro™ 极清视频编解码器，以及支持多种接口标准的显示控制器组成，以上产品可无缝协同工作以提供最优的PPA（性能、功耗和面积）。此外，基于芯原ZSP®（数字信号处理器核）技术的高清音频/语音平台和支持低功耗蓝牙（BLE）、Wi-Fi、NB-IoT和5G技术的多频多模无线基带平台为极低功耗和极高性能应用提供了可伸缩的架构。芯原增值的混合信号IP组合则可打造支持语音、手势和触摸界面的高能效自然用户界面(NUI)平台。芯原成立于2001年，总部位于中国上海，目前在全球已有超过600名员工。芯原在全球共设有5个设计研发中心和9个销售和客户支持办事处。 媒体垂询： 杨颖（Jessie Yang） (021) 8029 6826 [email protected] 石燕 （Sherry Shi） 86 15900477699 [email protected] 邢芳洁（Jay Xing） 86 18801624170 [email protected]
GLOBALFOUNDRIES and VeriSilicon To Enable Single-Chip Solution for Next-Gen IoT Networks July 13, 2017Integrated solution leverages GF’s 22FDX® technology to decrease power, area, and cost for NB-IoT and LTE-M applications Santa Clara, Calif. and Shanghai, China, July 13, 2017–GLOBALFOUNDRIES and VeriSilicon today announced a collaboration to deliver the industry’s first single-chip IoT solution for next-generation Low Power Wide Area (LPWA) networks. Leveraging GF’s 22FDX® FD-SOI technology, the companies plan to develop intellectual property that could enable a complete cellular modem module on a single chip, including integrated baseband, power management, RF radio and front-end module combining both Narrowband IoT (NB-IoT) and LTE-M capabilities. The new approach is expected to deliver significant improvements in power, area, and cost compared to current offerings. With the proliferation of connected devices for smart cities, homes, and industrial applications, network providers are developing new communications protocols that better meet the needs of emerging IoT standards. LPWA technology takes advantage of the existing LTE spectrum and mobile infrastructure, but focuses on delivering ultra-low power, extended range, and much lower data rates for devices that transmit small amounts of infrequent data, such as connected water and gas meters. The two leading LPWA connectivity standards are LTE-M, which is expected to get traction in the U.S. market, and NB-IoT, which is gaining ground in Europe and Asia. For example, the Chinese government has targeted NB-IoT for nationwide deployment over the coming year. The combination of these two technologies is expected to push cellular M2M module shipments to nearly half a billion by 2021, according to ABI Research. GF and VeriSilicon are developing a suite of IP to enable customers to create single chip cost- and power-optimized solutions for worldwide deployment, based on a dual-mode carrier-grade baseband modem with integrated RF front-end module. The design will be fabricated using GF’s 22FDX process, which leverages a 22nm FD-SOI technology platform to provide cost-effective scaling and power reduction for IoT applications. 22FDX is the only technology that allows efficient single-chip integration of RF, transceiver, baseband, processor, and power management components. This integration is expected to deliver more than an 80 percent improvement in both power and die size compared to today’s 40nm technologies. “Our 22FDX technology is perfectly positioned to support the explosive growth of low-power, battery-operated IoT devices,” said Alain Mutricy, senior vice president of product management at GF. “We are especially excited about the opportunities presented by the China market, which is leading the way with a nationwide commitment to IoT and smart cities. This new initiative expands on our long standing relationship with VeriSilicon—an important partner helping us build an FD-SOI ecosystem around our new 300mm fab in Chengdu.” “Started from more than five years ago, as a Silicon Platform as a Service (SiPaaS) company, VeriSilicon has developed FD-SOI IPs and achieved first silicon success of many chips based on FD-SOI technologies. For IoT applications, besides cost advantages, integrated RF, body bias, and embedded memory, such as MRAM, are the key benefits of FD-SOI technologies beyond 28 nm bulk CMOS.” said Wayne Dai, VeriSilicon Chairman, President and CEO. “Integrated with RF and PA on GF 22FDX, the baseband and protocol stack are being implemented on our energy efficient and programmable ZSPnano that is optimized for control and data flow with powerful low latency, single cycle instructions for signal processing. GF’s new 300 mm fab for FDX in Chengdu and IP platforms such as this single chip solution for integrated NB-IoT and LTE-M, will have significant impact on China IoT and AIoT (AI of Things) industries.” GF and VeriSilicon expect to tape out a test chip based on the integrated solution, with silicon validation in Q4 2017. The companies plan to pursue carrier certification in mid-2018. About GF: GLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. GLOBALFOUNDRIES is owned by Mubadala Development Company. For more information, visit https://www.globalfoundries.com. About VeriSilicon VeriSilicon Holdings Co., Ltd. (VeriSilicon) is a Silicon Platform as a Service (SiPaaS®) company that provides comprehensive System on a Chip (SoC) and System in a Package (SiP) solutions for a wide range of end markets including mobile internet devices, datacenters, the Internet of Things (IoT), automotive, industrial, and medical electronics. Our machine learning and artificial intelligence technologies are well positioned to address the movement to “intelligent” devices. SiPaaS provides our customers a substantial head start in the semiconductor design and development process and allows the customers to focus efforts on core competency with differentiating features. Our end-to-end semiconductor turnkey services can take a design from concept to a completed, tested and packaged semiconductor chip in record time. The breadth and flexibility of our SiPaaS solutions make them performance effective and cost efficient alternatives for a variety of customer types, including both emerging and established semiconductor companies, Original Equipment Manufacturers (OEMs), Original Design Manufacturers (ODMs), and large internet/cloud platform companies. VeriSilicon’s camera-in, display/video out pixel processing platform includes high-fidelity ISP, embedded Vision Image Processor (VIP) with machine learning acceleration, Vivante® low power GPU and high performance GPGPU, Hantro® ultra high definition video codec, and rich featured display controller, which work seamlessly together to deliver best PPA (Performance, Power, Area). In addition, based on our ZSP® (digital signal processor) technologies, HD audio/voice platforms and multi-band/multi-mode wireless baseband platforms including BLE, Wi-Fi, NB-IoT, and 5G provide scalable architectures for both ultra-low power and extremely high performance applications. Our value-added mixed signal IP portfolio enables energy efficient Natural User Interface (NUI) platforms for voice, gesture and touch. Founded in 2001 and head-quartered in Shanghai, China, VeriSilicon has over 600 employees with five R&D centers and nine sales offices worldwide. Contacts: Jason GorssGF(518) 698-7765[email protected] Miya KongVeriSilicon+86 21 51311118[email protected]
