Silicon Photonics: A Marriage of Optical and Digital on GF’s RF Process

GlobalFoundries and SiPh startup Ayar Labs have been collaborating since 2016 on a monolithic solution for in-package optical interconnects

“It requires a very delicate balance to have the photonics and the RF CMOS circuits on the same chip. By integrating it all into silicon, we are taking advantage of the scale, costs, and process control of silicon manufacturing.” – GF Vice President Anthony Yu

By Dave Lammers

When GlobalFoundries (GF) acquired IBM Microelectronics in 2015, it received access to a treasure trove of R&D in silicon photonics (SiPh), work that is now moving into the general availability phase on 300mm wafers. The ramp-up comes in time to make a single-chip SiPh design from a key partner, California-based startup Ayar Labs, which has created a monolithic design that sets new benchmarks for package-to-package interconnect in terms of bandwidth, power consumption, and latency.

Anthony Yu, vice president of GF’s Computing and Wired Infrastructure Business Unit, said GF took IBM’s nine years of photonics research and “industrialized” the 90nm process, known as 90WG. “We made it work in Fishkill on 300mm wafers, and it is in production now. What GF has done is to position ourselves as a high-volume producer of transceiver parts,” he said.

For several years GF has been building components for optical transceivers with its silicon-germanium process (9HP) at its Fab 9 near Burlington, Vermont. Those solutions – laser drivers, transimpedance amplifiers (TIAs), and other discrete components – are used in the “pluggable” multi-chip photonics modules used in data centers and other markets to connect racks of servers via fiber links across mid-range distances.

GF’s 45CLO process combines digital RF functions with the optical devices required
for a SiPh monolithic solution. (Source: GLOBALFOUNDRIES)

Optical connections are set to move to a new phase, in which the pluggable optical transceivers are replaced by having the photonics link connected to a high-performance IC in the same package, with an external laser providing the light source. That package connects over fiber to another module with a photonics link, creating package-to-package interconnects at high speeds and much lower power consumption.

Called MIPO for monolithic in-package optics, MIPO I/O integrates Ayar Labs’ opto-electronic chiplets, named TeraPHY, inside a multi-chip package (MCP). The MIPO I/O chiplets from Ayar Labs are in the engineering sampling stage now, after several years of collaborative work with GF. Intel, a pioneer in the silicon photonics field, is an early adopter of the Ayar Labs solution, with an initial goal of connecting its FPGAs (field-programmable gate arrays) with other modules.

Yu said while there are other startups in the field, and the giant data center companies are working on their own designs, Ayar Labs is “one of early designers of a terabit solution. They are very progressive and highly collaborative,” adding that he believes the Ayar Labs monolithic chiplets are “an industry game-changer.”

High-volume manufacturing is one key to creating
cost-effective photonics solutions. (Source: Ayar Labs)

Putting the photonics functions on the same chip as the electronic control circuitry is an interesting challenge. The chips combine the electrical interface, the digital circuitry, and the high-speed analog mixed-signal circuits with the optical components on the same piece of silicon. “It requires a very delicate balance to have the photonics and the RF CMOS circuits on the same chip. By integrating it all into silicon, we are taking advantage of the scale, costs, and process control of silicon manufacturing,” Yu said, adding that the GF-Ayar Labs team paid close attention to the challenges inherent in packaging, assembly, and test.

An Inflection Point

Mark Wade, president, CTO and co-founder of Ayar Labs, said the company was created in 2015 by members of a collaborative multi-university photonics project. The next year, the startup established its partnership with GF. “The industry was at an inflection point. Everyone saw the fundamental limitations of electrical I/O, and predicted that the bag of tricks (to extend electrical interconnects) would go empty around right now,” Wade said, adding that 112 Gbps may be the end of the line for CMOS-based Serdes connections.

Ayar Labs started working on a new solution from the ground up, setting its sights on using optics to fundamentally solve the chip-to-chip bandwidth problem. Optics require far less energy, and can achieve much higher bandwidth, and lower latencies, compared to electrical interconnects. Once into an optical fiber, it does not suffer the distance/bandwidth tradeoff that impacts electrical interconnects.

[For a detailed discussion of the Ayar Labs solution, see: Optical I/O Chiplets Eliminate Bottlenecks to Unleash Innovation]

As Ayar Labs and GF were working on a single-chip solution that would take advantage of high-volume manufacturing, data centers were running out of bandwidth. Machine learning, for example, involves connecting processors and GPUs and high-bandwidth memory in ways that require higher chip-to-chip bandwidth. “The data centers want physically distributed machines, using various components connected with very-high-bandwidth interconnects,” Wade said. “They want to architect new types of systems that are not possible with the current and next generations of I/O.”

The 45CLO process will enable best-in-class optical
as well as digital functions. (Source: GLOBALFOUNDRIES)

RF CMOS Advantages

GF and Ayar Labs collaborated on ways to optimize GF’s 45 RF SOI process for the optical structures and other functions. That technology, developed for the mmWave market, was modified to include photonic function and is now being used to build prototypes.

Wade said the RF SOI CMOS is an “enabling thing, because it allows us to build both transistors and optical devices in the same planar layer. And the SOI process enables extremely fast transistors, faster than most of the advanced nodes built today. They don’t have the same density as the advanced (bulk CMOS) nodes. But In terms of analog performance and Ft and Fmax speeds, they outperform the advanced FinFET nodes that people are using for digital.”

Ayar Labs and GF are working together on GF’s next-generation silicon photonics platform, called 45CLO, which Ayar Labs plans to use for volume production of its parts. “We are working on several things with GF to take the work that we’ve done in pilot production on the 45nm RF SOI, combine it with some of the technologies and processes that GF has from the IBM R&D acquisition, and mix those together to build a highly reliable and manufacturable process to build our solution in 45CLO,” Wade said.

GF’s Yu said the company’s 45CLO monolithic technology will be manufactured at Fab 8 in Malta, New York and plans on qualification of its production process in the second half of 2021.

Ayar Labs CEO Charlie Wuischpard, who was a vice president and general manager in Intel’s Data Center Group before joining Ayar Labs in November 2018, said one optimization in the 45CLO process is a germanium module that “will enable higher performance and allow us to build a really high-performance photo detector. We think the result will be best-in-class optoelectronic performance.”

Wuischpard said integrated optical interconnects can enable dramatic capabilities in new system architectures. “We are still at the early stages of building an optical I/O inside of a CPU package. We need to think of the post-exascale machines. Not today’s supercomputers, but tomorrow’s supercomputers and AI systems.”

From Point A to Point B

Patrick Moorhead, founder, president, and principal analyst of consultancy Moor Insights & Strategy, said “the only way you can make AI and Machine Learning work is to have more data, and that data has to get from point A to point B, and it has to do that very quickly. And it has to get there, in many circumstances, with low latency.”

 Cloud gaming, robotics, robotic surgeons, CV2X car-to-car and car-to-network links, Smart Manufacturing, cellular networks, and other applications, require data centers to handle much larger amounts of data while keeping their energy consumption under control. “We are creating a lot more data at the edge. Whether it is driven by mobility, IoT, or 5G, we are going to have a trillion points out there, and many of them are going back to the data center,” Moorhead said, adding that it is “because of machine learning and AI that we will be able to do useful things with all of that data.”

The industry has reacted to the slowing down of Moore’s Law scaling by turning to heterogeneous computing, using ingenious forms of packaging and chip stacking. As a way to connect one chip with another, silicon photonics could prove to be an attractive option. Photonic links to high-bandwidth memory or accelerators could be more attractive than, for example, using through silicon vias (TSVs), which limit design flexibility.

“Silicon photonics is a new way to have chips talk to each other, using optical links that have the same performance as a PCI Express card or 3D packaging. And at the right volumes, using silicon photonics for off-chip acceleration will be less expensive in the long run,” Moorhead said.

Read Pat’s recent article in Forbes on how GLOBALFOUNDRIES quietly became a force in silicon photonics.

A module including TeraPhy chiplets can connect optically at
higher speeds and lower power. (Source: Ayar Labs)

Optical Provides Some Relief

Bob Wheeler, principal analyst at The Linley Group, said the TeraPhy chiplet from Ayar Labs has 10 optical ports, and takes advantage of wavelength-division multiplexing (WDM) to increase the number of optical signals on a single fiber.

“That has allowed them to pack a lot of bandwidth on the beach front, the linear edge on the face of the chip. At the end of the day how much bandwidth you can get off [the chip] becomes the limiting factor, particularly for an Ethernet switch where you are trying to get tens of terabits on and off.

“What they’ve done is unique in terms of the level of integration and WDM. How they did the implementation, getting the chiplet so small, comes from the Ayar Labs proprietary technology for the modulators and detectors, which are quite tightly packed compared with traditional Mach-Zehnder modulators,” Wheeler said.

Any major technology transition takes time, and Wheeler said optical I/O could start with next-generation Ethernet chips and then migrate to high-end processors and ASICs. “When electrical I/O runs out of steam, optical I/O is the only one to provide some relief.”

Yu, vice president at GF, said silicon photonics – and the optical chip-to-chip connections it enables – will continue to drive platform innovation and new solutions for years to come. With its manufacturing excellence, its deep expertise in SiPh, and the current momentum of its 45CLO monolithic process, GF is positioned to be an industry leader in this space.

“People have been talking about the introduction of silicon photonics for over a decade,” Yu said. “What silicon photonics has going for it, and what GF has in its favor, is to bring value through large scale manufacturing. We have the ability to use 300mm manufacturing, with very tight process controls, to marry the optical and silicon functions in VLSI solutions. We bring our clients an ability to scale their solutions for rapid uptake.”

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