June 15, 2017By: Timothy Saxe Most electrical engineers are familiar with FPGAs, and many have had experience using standalone FPGAs. eFPGA (embedded FPGA) technology allows a semiconductor company to embed an FPGA in an SoC or ASIC. The industry knows from bitter experience (40 defunct FPGA startups and counting) that programmable logic is not easy. The main stumbling block for FPGA startups has been the design environment, not the silicon. The simple fact is that the silicon is only as good as the tools that support it – they must be straightforward, robust, easy-to-use, and deliver excellent quality of results. As if that were not challenging enough, eFPGA products also exist in the ASIC design environment which uses a different tool flow. Thus a successful eFPGA must have an excellent silicon implementation, excellent ASIC tool support, and an excellent FPGA tool flow. Fortunately there are major benefits to embedding FPGA: lower power, higher performance, lower cost, improved future proofing and design flexibility. QuickLogic started life 29 years ago producing standalone FPGAs. 15 years ago we saw that the economics had changed to favor mixing ASIC cores with programmable logic, and we started down the road of developing embedded FPGA solutions. At that time, various FPGA startups were trying to sell eFPGA technology, but there was no uptake. The reason there was no uptake was economic: masks were cheap, ASIC gates were cheap and FPGA logic was expensive. Roll the clock forward 15 years, and now things have changed: masks are expensive, ASIC gates are cheaper and FPGA logic is also cheaper. Our latest device, the EOS™ S3 System-on-Chip (SoC) targets the smartphone, wearable, and hearable markets. These are very price sensitive and power sensitive products. Fortunately the GLOBALFOUNDRIES 40nm cost structure allows us to meet the price requirements with a product that has enough eFPGA to be really useful. This enabled us to have a cost effective product where the hardware can be adapted for different markets without incurring mask costs. In addition, having eFPGA allows us to move critical tasks from software into hardware to save power, which is critical for power sensitive applications. A small digression on the meaning of power sensitive: everyone claims to be power sensitive. To server designers using a 25Watt FPGA to offload a 90Watt CPU is being power sensitive. In the wearable market where people want six months from a CR2450 battery the average system power must be 410uW, and in the IoT market where people want three years from two AA batteries, the average system power must be 318uW. Our focus is on the wearable and IoT markets, where designers expect the compute unit to use only 25% of the system power: 100uW for wearables, and 80uW for IoT. Since we operate in markets that require low power, we see GLOBAFOUNDRIES 22FDX® process as the workhorse of the future for power sensitive markets. The economics are better, and dynamic back-bias should enable designers to reduce average system power by 25% to 50% compared to 40nm. Particularly important to IoT, the eMRAM, coming soon to 22FDX, enables both single chip devices as well as ultra-low power sleep states more cost effectively than flash memory. Why now? What has changed in the past 15 years? First, the bets are getting bigger: the combination of mask costs and software costs have soared. Second, markets are more fragmented, which means lower volumes per design. Finally, future growth lies in IoT, which seems to mean a lot of different things. Now if you have a crystal ball that accurately predicts the future, you can simply produce an ASIC that meets those needs. But if you don’t, including a QuickLogic ArcticPro™ eFPGA block in your design will let you: Update your hardware when standards update or evolve Update your features when you discover new market needs Create multiple product variants from a single mask set Get to market more quickly, and stay in market longer by evolving product features Over the years, we have found that this is the hardest point to grasp. Talk to the ASIC team and they will tell you, correctly, to just tell them what you need and they can implement it better. The disconnect is that they are not responsible for defining what is required. Now you have another option. Include a small block of eFPGA – you will find it surprisingly economical in 22FDX. QuickLogic has been doing this for 15 years, so we understand what it takes for a successful integration – our methodology makes it no harder than adding any other hard macro. We also understand what a production quality FPGA design flow looks like – we’ve been supplying them to the most quality and reliability-conscious markets in the world – aerospace, defense, and instrumentation & test markets for 30 years. We understand really low power – we’ve been doing that for five years, and FD-SOI is the perfect complement to the ArcticPro architecture. Finally, eco-system is vital to the diverse needs of IoT, and the GLOBAFOUNDRIES FDXcelerator™ brings together a diverse collection of proven IP, such as our ArcticPro eFPGA, that enables silicon architects to rapidly develop high value, low power systems-on-a-chip. About Author Timothy SaxeSenior VP of Engineering and CTO Timothy Saxe (Ph.D) has served as our Senior Vice President and Chief Technology Officer since November 2008. In August 2016, he expanded the role to include Senior Vice President of Engineering. Mr. Saxe has been with QuickLogic since May 2001 and during the last 15 years has held a variety of executive leadership positions including Vice President of Engineering and Vice President of Software Engineering. Dr. Saxe was Vice President of FLASH Engineering at Actel Corporation, a semiconductor manufacturing company. Dr. Saxe joined GateField Corporation, a design verification tools and services company formerly known as Zycad, in June 1983 and was a founder of their semiconductor manufacturing division in 1993. Dr. Saxe became GateField’s Chief Executive Officer in February 1999 and served in that capacity until GateField was acquired by Actel in November 2000. Mr. Saxe holds a B.S.E.E. degree from North Carolina State University, and an M.S.E.E. degree and a Ph.D. in electrical engineering from Stanford University.