By: Manuel Sellier

There is a consensus that “bleeding edge” technologies, i.e. the continuation of Moore’s law whatever the cost of the technology, is bringing less and less return on investment for most players in the semiconductor industry. In this context there is a critical need for more innovations beyond traditional CMOS scaling. There are many opportunities for innovation in the value chain from semiconductor materials and devices to services, but the simplest one starts with substrates.

RF SOI and FD-SOI are great examples of how the industry is pushing differentiation with substrates to develop new standards for RF communication and low power computing. GLOBALFOUNDRIES has been a successful pioneer in this strategy. First, RF SOI has become the de-facto technology for a large number of components of the Front End Module (FEM) in cellular phones. From almost nothing 10 years ago, today the total market for RF SOI is around 1.5 million wafers (8 inch equivalent). Second, FD-SOI is now the technology of choice for mmWave RF-CMOS connectivity and battery powered devices requiring a very high level of energy efficiency. We will review, in this post, how Soitec is supporting GF with outstanding RF SOI substrate solutions.

How SOITEC supports GF with differentiated RF SOI technology

5G will rapidly change the way people and objects around the world communicate; GF and Soitec are supporting this change providing innovative technologies that support the evolution towards 5G and its coexistence with other existent and future standards.

Different communicating devices (vehicles, smartphones, “things”) RF Front Ends require differentiated technologies that could offer the right cost/performance trade-off facilitating their introduction and adoption. Soitec offers two families of RF SOI substrates: HR-SOI using a high resistivity base substrate and RF Enhanced Signal Integrity TM (RFeSI) SOI which adds a trap rich layer on top of the high resistivity base helping deliver on stringent linearity requirements – both of which are compatible with standard CMOS processes and foundries.

These two families of substrates are available in 200 and 300 mm diameters and offer different advantages in terms of linearity, insertion loss, isolation, noise figure and other key specifications and therefore can be used to design and manufacture different blocks and functions in the RF Front End. The examples here below are given as reference only as integration strategy differs largely among different RF Front End solutions providers.

• Antenna tuners, which require very high linearity are typically implemented on RFeSI substrates
• Receiver/ Transmitter switches requiring good linearity, low insertion loss, high isolation and high integration level can be manufactured on HR-SOI and/or RFeSI substrates
• Low noise amplifiers (LNA) on the receive path typically implemented in technology nodes below 90nmare commonly manufactured on 300 mm HR SOI wafers and if integrated with switches and other supporting blocks in 300 mm RFeSI ones.
• Power amplifiers could be fully integrated in 300 mm RFeSi substrates with switches and LNAs for connectivity, IoT and 3G/early 4G cellular applications

Thanks to a long-term strategic partnership GF and Soitec have been timely delivering products tailored to address the needs of a very demanding RF Front End market in continuous evolution.  This partnership extends in many fields including engineering and manufacturing, securing state of the art performance in high volume production.

Soitec is integrated into GF’s roadmap thanks to a shared vision of the market evolution. In the most recent example, GF’s next generation mobile and 5G RF Front End 8SW technology was designed to fully exploit the benefits offered by Soitec’s products.

In a semiconductor world where everybody is looking for differentiation, RF SOI and FD-SOI represent unique platforms delivering major advantages. RF SOI value is now fully recognized. It has been adopted by most of the players in the cellular FEM business. It will see continued growth with the increased complexity of radios at 4 and 5G. Soitec is committed to serve this industry with the right level of capacity and quality.

In our next post we will review how Soitec is supporting GF with outstanding FD-SOI substrate solutions.

About Author

Manuel Sellier

Manuel Sellier is Soitec’s product marketing manager, responsible for defining the business plans, marketing strategies, and design specifications for the fully depleted silicon-on-insulator (FD-SOI), photonics-SOI, and imager-SOI product lines. Before joining Soitec, he worked for STMicroelectronics, initially as a digital designer covering advanced signoff solutions for high-performance application processors. He earned his Ph.D. degree in the modeling and circuit simulation of advanced metal–oxide–semiconductor transistors (FD-SOI and fin field-effect transistors). He holds several patents in various fields of engineering and has published a wide variety of papers in journals and at international conferences.

By: Dave Lammers

Europe and Singapore are two sources of ideas for GF following the decision to pivot away from 7nm technology development. One company that sees strategic value in the 22FDX® solution is Synaptics.

While Tom Caulfield was trying to figure out how to re-position GLOBALFOUNDRIES as a differentiated foundry, Rick Bergman, the CEO of Synaptics, had concluded that GF’s 22FDX process could do exactly that: differentiate Synaptics in the market for artificial intelligence-enabled Internet of Things applications.

“For the very large customers that we have, we are banking on 22FDX for unique solutions specifically for the IoT market,” Bergman said in a keynote address at the foundry’s annual technology conference, GTC 2018, in Santa Clara.

Synaptics Adopting 22FDX

Synaptics, with revenues of roughly $2 billion this year, focuses on the human-machine interface (HMI), a market that is rapidly moving to voice-enabled interfaces. On-chip neural network processing in IoT edge devices is a key enabler, requiring the right mix of performance, power consumption, and cost.

Bergman said one Synaptics chip has taped out in the fully depleted silicon-on-insulator (FD-SOI) 22FDX process, another is “right behind it, aimed at voice and video,” while a third chip will support augmented reality and virtual reality (AR/VR) capabilities.

The company evaluated 28nm bulk transistors and found that “they didn’t have the horsepower required,” he said, while advanced FinFET-based leading-edge processes “require a certain amount of (design) investment, and in many cases the volumes don’t justify it in a fragmented market like IoT.” GF’s non-volatile memory solutions were another factor, he added.

Edge IoT devices increasingly are being used to process AI workloads, rather than sending them to the cloud. For IoT edge solutions, Bergman said Synaptics requires “extremely low power,” using FDX’s forward and back-biasing capabilities to switch to high performance, when needed, for products such as smart speakers.

“With biasing, we can gain performance when we need it, and when we don’t need it we have very low power. Since IoT tends to be a very competitive market, cost is an important factor as well,” he said.

Learning from Europe….

After being named CEO of GF in early March, Caulfield began visiting customers, including the major European semiconductor companies. These companies had looked at the rising costs of leading-edge designs, the slowing improvements to Moore’s Law scaling, and made their own pivots.

“They learned that leading edge is not the only game in town, that innovation is shifting toward the creation of differentiated features. They have prospered as a result. I came away from there knowing what we had to do to differentiate ourselves. And I knew we had to get out of our mind the idea that we had to have leading-edge technology to be strategic to these customers,” Caulfield said.

…And from Singapore

Caulfield said he wants the larger GF to learn from the foundry’s Singapore operation, which has mastered the skills needed to ensure zero defects, provide improvements to its technology platforms, and hone manufacturing discipline: achieving high yields on a wide variety of products while keeping the fabs full.

“Much of our revenue in differentiated silicon comes from Singapore,” he said, adding that “the revenue model for GF is Singapore.”

He made the point that many people are fixated on leading-edge technologies, currently 7nm and beyond, with relatively little attention given to the many advances in power, MEMs, RF, and other technologies. The heart of the day-long GTC 2018 was spent describing the innovations which differentiate GF in those areas. GF’s technologists are coming up with ways to boost the performance of the 12nm FinFET process, adding options such as high-voltage and NVM offerings. By halting 7nm logic development, executives promised that more of the foundry’s resources will be available for power, analog, IoT, automotive, and other markets which have their own technology differentiations.

Three Ways GF is Different

During a coffee break, I asked Subramani Kengeri, vice president of client solutions, if the pivot away from 7nm might leave GF fighting for business with foundries such as Taiwan’s UMC or China’s SMIC.

Kengeri said GF differs from its competitors in three ways: first, the breadth of offering and level of technology differentiation is much greater. In automotive, eNVM, HV, mixed-signal, FinFET, Silicon Photonics and several other key areas, GF simply offers a much richer and more complete technology portfolio than other foundries. With its FDX technology, it offers a unique solution. In RF it dominates. “Thinking RF? Think GF,” was a clever refrain heard from Bami Bastani, senior vice president of GF’s business units.

Secondly, Kengeri said GF has superior packaging technologies, and going forward will have more resources to invest in packaging to support growing needs for heterogeneous integration. And thirdly, GF — having acquired Chartered Semiconductor and IBM Microelectronics and grown to $6 billion in revenues — is a more global company than its competitors, with fabs in United States, Germany, and Singapore, and a strong global client solutions team.

Caulfield said with the pivot decision behind it, GF is focused on improving manufacturing efficiencies and boosting fab utilization rates, while adding capacity where needed in RF, power, automotive, and other fast-growing markets. “We want to fill the assets that we have,” he said.

 
GF will continue to invest to create further new features on these offering platforms

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.

By: Dave Lammers

A couple of nanometers counts for a lot in today’s semiconductor industry. In an earlier era, foundries would offer a half-node by performing a “litho shrink,” without many changes other than pushing the mask and stepper configuration.

GLOBALFOUNDRIES move to a 12LP process is much the opposite, using the same patterning as on the still-going-strong 14LPP platform but with many subtle changes to the process and standard cell library to achieve improvements in performance, power consumption, and area (PPA). First announced in September 2017, with public support from Advanced Micro Devices (AMD), the details of the process changes came to light in a presentation at the 2018 Symposium on VLSI Technology, held in Honolulu in late June.

On the business side, GF has prepared automotive and RF/analog modules to better support those markets with its 12LP offering. The 12LP process got a major boost last autumn when AMD said it would quickly move major product lines to the 12LP process. Then a mobile customer began using 12LP for its application processors.

Erin Lavigne, deputy director of leading edge FinFET offering management at GF, said “most of the customer interest is in 12LP going forward.” Customers that are designing new ICs go for the higher transistor density, power and performance gains, with cost savings coming from smaller die sizes.

Because the tool set is virtually the same, the manufacturing corridor can be “flexed” for either 14LPP or 12LP production. “Our capacity is fungible,” Lavigne said. “While AMD is a key strategic customer of ours, Fab 8 is not full with just AMD. We can support all of our customers, while continuing to support AMD’s needs. Besides our two lead customers, the pipeline has exploded in fast followers in consumer, AI, automotive, and industrial segments,” Lavigne said.

Hsien-Ching Lo, a GF technology development deputy director, said in one important area — the back end of the line (BEOL) — GF has taken a different approach from its foundry competitors. While other foundries have reduced the M2 pitch to achieve die size reductions, the GF 12LP employs the same 64nm M2 pitch as its 14LPP process. That strategy allows customers to gain in performance, power, and area (PPA) “while minimizing design rework.”

Supporting evidence for that statement came at the VLSI conference in Hawaii. A Samsung Foundry presentation of its 11LP process described an ability to use either a 9T or 6.75 track library. The 6.75T library, however, requires using a 48nm pitch M2, compared with the 64nm M2 pitch of its 14nm process. TSMC has taken a similar tack, changing the M2 pitch for its 12nm offering, which is a follow-on to its 16nm process.

Lo said moving to a different M2 pitch is a design rule change that requires much more design rework than the GF strategy of supporting its 7.5 track library with the same M2 pitch. “It is much easier for our customers to migrate from 14 to 12. They can get a performance and area benefit, with a very small design migration,” he said.

While GF continues to support the 14LPP 9T library for 12LP designs, Lavigne said the 7.5-track library “offers the most bang for the buck” in both die size reduction and higher performance. “There is some redesign for customers to use that library. They can choose how much redesign they want to do to extend the platform.”

Compared with the GF 14LPP process, the 12LP with performance elements delivers a 15 percent faster ring oscillator AC performance, 16 percent less total power for the 12LP (with the 7.5T standard cell library) at equivalent speed, and 12 percent logic area scaling. Notably, the 12LP SRAMs benefit from a 30 percent leakage reduction at the same read current.

Lo took the stage at the VLSI symposium to describe the five process element modifications in the 12LP process.

The fin profile was improved to a taller, thinner fin, improving the drive current and short channel control. Also, the fin surface roughness was reduced, resulting in a carrier mobility increase of 6 percent for the NFET and 9 percent for the PFET.

To improve the PFET performance without increasing leakage, the source/drain cavity profile was modified, moving from a bowl-shaped cavity in the 14LPP process to a deeper cavity in the 12LP process. The enlarged cavity is needed to improve the strain on the channel, delivering more embedded silicon germanium (eSiGe) but without the penalty of higher leakage.

Thirdly, the eSiGe was optimized to improve pattern loading effects, with a 4 percent improvement to the 40-fin devices and a 5 percent improvement to the single diffusion break (SDB) devices.

Fourthly, the NFET doping density was increased. By optimizing the silicon-phosphorus epitaxial process, the source-drain resistance was improved by roughly 6 percent, Lo said.

Contact resistance is a major concern at leading-edge design rules. GF’s Advanced Technology Development team exercised dual optimizations to reduce the contact resistance. The trench contact profile was improved by enlarging the bottom contact size. “We wanted to enlarge the contact area and the bottom CD (critical dimension), but without a penalty in terms of TDDB (time dependent dielectric breakdown). Typically, with an increase in the contact CD, the space between contact to polysilicon gate becomes smaller. Then you can see a degradation in the dielectric breakdown,” Lo said in an interview at the VLSI symposium.

Also, the doping profile under the trench contact was optimized to reduce the contact barrier height. And the silicide resistance was improved by “some interface engineering,” he said.

On the surface of it, going from 14nm to 12nm may not seem to be such a big deal. But scratch the surface, and a lot of engineering work went into delivering a compelling technology.

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.

By: Fisher Zhu

Editor’s Note: This article was previously published in EET China

In Chinese, the use of the word “cooking heat” is not limited to the kitchen; it can also be used to describe someone’s character and maturity.

This also applies to the semiconductor manufacturing industry.

Although a tiny chip looks quite simple, it embodies volumes of scientific knowledge. Only those who truly understand manufacturing processes and application principles know how hard it is to produce a chip, and can appreciate the beauty behind paying attention to small details.

Wafer manufacturing and the cars of the future

Thanks to the unstoppable advancement of semiconductor technology, many incredible automotive functions involving semiconductor technology are being developed; for instance, advanced driver assistance systems (ADAS) are currently paving the way for self-driving cars.

Generally speaking, from now until 2023, the auto applications semiconductor market is expected to grow at a 7% compound annual growth rate, and the market’s value will increase from $35.0 billion to $54.0 billion. Thanks to the impetus from ADAS/self-driving/in-vehicle infotainment (IVI)/electric vehicle powertrain/safety applications, the value of semiconductor chips in every car is projected to rise from $375 in 2017 to $613 in 2025. During this period, the value of the ADAS applications is expected to surge, with an estimated CAGR of 19%.

But in spite of this situation, the vast majority of people are unaware of the increasingly close connection between auto electronics and semiconductor foundries.

IP, process technology, and service are all vital

As for GF’s auto electronics business, the AutoPro™ service package is a critical element. This service package offers the experience, quality, and reliability services for all GF’s automotive technologies. As a result, the service package can satisfy the automotive industry’s strict quality and reliability requirements, and help car manufacturers to use the power of semiconductors to enter the new “smart Internet” age.

The importance of the AutoPro service package solution lies in the way it enables all of GF’s worldwide fabs, including Dresden, Germany; Malta, New York; Singapore; and Chengdu, China, to provide modularized platforms that have passed auto specification certification for various types of automotive clients regardless of which processes they’ve selected to use (e.g., Singapore’s mainstream 180nm, 130nm, 55nm, and 40nm processes, Malta’s 14LPP/12LP/7LP FinFET, or Dresden’s 22nm FD-SOI technology).

Not surprisingly, automotive makers have even higher quality and reliability requirements than clients in other markets. That is why there is a significant importance of having IATF16949 certification.

IATF16949 certification represents confidence that the entire production process is maintained in a controllable, traceable state. It also guarantees that auto-grade IC production, testing, and screening processes have zero-defect status, and is therefore an essential indicator for automotive clients.

GF’s Dresden Fab 1 was recently completed and received its first full-scale IATF16949/ISO9001 certification, which indicates that the plant’s quality management system complies with automotive production requirements, and motor vehicle clients can obtain automotive-specification IC products from GF’s platform.

Selecting the correct process for different applications

Unlike other foundries, GF has entered both FD-SOI and FinFET areas. GF’s 22FDX®, which is part of the AEC-Q100 automotive standard, has already achieved certification, and can satisfy the strict quality and performance requirements of the motor vehicle market.

We have consistently felt that the cost and complexity of the mask process in the production of 22FDX are significantly lower than in the 14nm FinFET process, and the FinFET process also cannot easily achieve the body bias needed by RF devices. As a consequence, by achieving real-time trade-offs between power consumption, performance, and cost, FD-SOI offers an ideal technology for new embedded systems with linking ability. The Internet of Things (IoT), 5G, and ADAS are the most suitable markets for FD-SOI technology. In contrast, an advanced CMOS technology such as FinFET is suitable for chips designed to offer maximum processing performance.

How does one select the suitable process for different applications?

GF has always focused on maintaining close ties with clients and fully understanding their product needs. If a client wants to produce a high-performance processing chip, GF will recommend that they use the FinFET process; if they only want to produce a radar receiver, then the Si-Ge process will be sufficient; and if they want to produce high-resolution radar, the 22FDX process is the most appropriate. And while formulating solutions, GF also helps clients make the right choice by providing PPA analysis reports corresponding to different processes.

Taking automotive radar as an example, the RF unit of current 77-86GHz medium-/long-range automotive radar is usually based on the Si-Ge process, and the digital unit is based on the 180nm and 130nm CMOS process; as a result, the chip’s overall processing capability is poor. In comparison, GF’s 22FDX technology can provide outstanding millimeter wave performance and digital density, which can enable radar sensors based on 22FDX to provide even higher resolution and lower latency, while ensuring extremely low overall system cost. We have seen clients quickly introduce radar imaging chipsets based on 22FDX technology. These chipsets can detect objects within a range of 300 m, and offer a wide field of view with extremely high resolution.

And clients have been using GF’s mainstream CMOS process technology in the development of 77GHz short-/medium-range radar modules. These modules integrate microcontrollers, digital signal processors, SRAM, flash, and support components on individual circuit boards, and can be used to replace large radar arrays.

Of course, radar is only one way that semiconductors are being used in cars. Powertrain control is another way. At the recent Embedded World conference, Silicon Mobility displayed its Field programmable control unit (FPCU), which can be used to control electric and hybrid auto powertrains.

This element was designed to use GF’s 55LPx technology, can process information from and control sensors and actuators in real-time, and can be linked with a standard CPU on a single chip (complies with ISO 26262 ASIL-D safety standards).

A framework based on this FPCU will offer greater functionality, flexibility, and safety, and can boost powertrain control ability and performance in electric and hybrid cars. By employing hardware, not software, to quickly implement complex powertrain control algorithms, this framework can conserve energy and prolong battery life. According to Silicon Mobility, the FPCU can extend the range of electric and hybrid cars by 32%.

At present, MCUs used for air conditioning, engine, and oil system control, short-/medium-/long-range radar, ICs used for electric/hybrid car power supply management, and high-performance processors used in ADAS/self-driving systems account for the leading  shares of GF auto electronics applications services. From our own observations, Chinese automotive clients tend to seek visual and self-driving processing chips, the biggest applications in the European market consist of microcontrollers, sensors, cameras, and lidar, and American clients are targeting lidar and self-driving solutions.

China is a very interesting market, and roughly 30% of semiconductor vendors in the international market are from China. However, many tier 1 auto manufacturers in China still purchase standard radar and processor chips from large motor vehicle device companies—this is the current state of affairs. Nevertheless, GF still sees great promise in the various innovative solutions that have emerged in China; one example of these is the application of visual monitoring system experience to the automotive field. Apart from providing built-in IP solutions such as MIPI interface and Can Bus, our strategy also includes a design center in China to help clients make even better use of GF platforms.

About Author

Fisher Zhu

Mr. Zhu has more than 15 year rich experiences in semiconductor industry. He held various positions in some leading companies, incl. R&D, system design, software and product management and marketing. He is now the China Marketing Director at GlobalFoundries, previously he worked with STMicroelectronics, Freescale and Synaptics.

Mr. Zhu holds the bachelor and master degree of E.E from Shanghai Jiao Tong University.

By: Gary Dagastine

By some estimates there are now more than 260 startups and established companies around the world scrambling to develop, qualify and bring to market chips and technologies for new ADAS (advanced driver-assistance systems) and autonomous driving applications.

Accordingly, venture capitalists, technology companies, carmakers, Tier 1 automotive suppliers and others are sharply ratcheting up their investments in this area. Venture capital investments alone in automotive and other AI-based applications grew to some $1.6 billion last year, up from $1.3 billion in 2016 and $820 million in 2015, according to research firm CB Insights.

What’s more, this activity is taking place globally. Among notable recent announcements was the news that Shenzhen, China-based self-driving start-up Roadstar.ai raised $128 million in Series A venture funding. It’s reportedly the single largest investment to date in a Chinese autonomous driving company, eclipsing the $112 million in funding announced earlier this year by another self-driving start-up, Guangzhou-based Pony.ai.

Why is interest in this space growing so strongly? On a consumer level, many drivers appreciate ADAS features like collision avoidance, blind spot warnings, adaptive cruise control and so on, and because carmakers want to satisfy their clients they are working to make these systems more sophisticated and increasingly available in cars at all price points.

On a societal level, driver-assistance/self-driving features have much more to offer. For example, there are about 40,000 deaths from motor vehicle accidents annually in the U.S. and over a million worldwide, with an additional 20-50 million people injured or disabled. Vehicles with greater autonomous capabilities have the potential to significantly reduce these numbers.

They also open up entirely new business opportunities, such as self-driving taxis.

A Brain on Wheels

The standards-setting organization SAE International has established a five-level classification system to describe the level of automation in cars, going from Level 1 (the system gives warnings but the driver drives the car) to Level 5 (fully autonomous operation with no human intervention required).

As the industry moves toward Level 5, sensors such as cameras, lidar and radar will generate torrents of data which must be processed, integrated and transmitted in real-time so that sophisticated deep neural-net-based machine learning algorithms can make use of it to recognize objects in the environment, predict their actions, communicate with other vehicles, and make vehicle-control decisions.

Some argue that this can be best accomplished with decentralized in-car network architecture, because it would be an evolution of existing ADAS systems and therefore would have the least impact on the design of automotive computing systems. It also would accommodate the use of specialized processors and allow new features to be added in a stepwise fashion.

The problems with this approach, according to Mark Granger, GLOBALFOUNDRIES Vice President of Automotive, are that while local processors and limited network bandwidth might be adequate for Level 2 (partial, or “hands-off”) or perhaps Level 3 (conditional, or “feet off”) operation, they lack the ability to handle in real-time the vast amount of data required by AI-based machine learning algorithms to enable truly autonomous operation.

“Decentralized architectures might provide up to 5 TOPs (trillion operations per second) and about 10 Mbits/s of in-car bandwidth,” he said. “But to operate at Levels 3-5, centralized network architecture with powerful, efficient processors that provide 50-100 TOPs and in-car data rates of 100 Gbits/s is needed. To put that in perspective, in the year 2000 the world’s most powerful supercomputer had the ability to do only 1 TOPs. So autonomous vehicles really will have to be brains on wheels, and a centralized architecture is the best way to achieve that.”

Until now the semiconductor technologies at the heart of ADAS/autonomous system development have been graphics processors (GPUs) and microprocessors (CPUs). But as developers move toward Level 5 automation, the proliferation of these chips in automotive systems becomes increasingly problematic, because while they are powerful they are also power-hungry.

“Self-driving cars are in their infancy, and unless something is done to reduce the power consumption of the processors in their AI-based systems, maybe they’ll never grow up,” said Granger. “The chips powering today’s versions of self-driving cars essentially require racks of server-class chips that draw maybe 7,000-10,000 watts of power. While that’s OK for development and testing purposes, it’s impractical for commercial products. Plus, you also have to consider the challenges and expense of cooling them, and they are relatively large physically. Everyone has a goal to get the power budget as low as possible for a given function.”

Enter GF’s ASICs

ASICs (application-specific integrated circuits) specifically designed to meet the needs of automotive systems not only can be both powerful and extremely energy efficient, but they also allow an automotive client to differentiate itself from the rest of the pack. They provide design flexibility and allow for designs that are much more powerful than current GPUs.

Large CPU clusters and hundreds of thousands of multiply and accumulate (MAC) circuits on each die meet the heavy computational requirements of AI algorithms, while gigabits of embedded SRAM and gigabytes of off-chip DRAM interfaces feed the hungry compute engine.

GF offers 14nm and 7nm FinFET ASIC system-on-chip (SoC) devices which deliver optimum combinations of power, size and energy efficiency versus both GPUs and competing ASIC technologies, while meeting automotive quality standards such as the functional safety standard ISO26262.

FX-14™ ASICs allow users to take advantage of an array of 64-bit and 32-bit ARM® cores for system design, along with a 56Gbps high-speed SERDES (HSS); an embedded TCAM memory capable of billions of searches per second; density- and performance-optimized embedded SRAM; and 2.5D packaging options that maximize application flexibility.

FX-7™ ASICs extend the offering with up to 112G HSS, the densest on-chip SRAM and a large number of off-chip DRAM interfaces (LPDDR, GDDR, HBM), including 2.5/3D packaging options that maximize application flexibility.

The GF ASICs differ from those offered by others not just in their capabilities, but also in their pedigree. The IBM Microelectronics acquisition in 2015 brought to GF one of the industry’s leading ASIC development teams, with more than 1,000 design engineers around the world and a history of some 2,000 completed ASIC designs for applications ranging from high-end servers for critical enterprise networks to low-cost gaming platforms.

“Our ASIC team has a proven track record on a range of products from highly complex electronics for servers and aerospace, to high-performance low-cost applications that covered all of the top gaming platforms,” said Igor Arsovski, Chief Technical Officer of GF’s ASIC business unit and GF Fellow.

“Unlike other design houses, we offer a broad array of IP that has undergone systematic and extensive model-to hardware correlation and HTOL stresses to both reduce design-to-tapeout cycle time and improve first-time right design success rate,” he said. “This rigorous methodology has ensured that even after tens of process nodes and over 2,000 ASIC designs we have never failed to deliver an ASIC to our client. Also noteworthy in the automotive context is the fact that our ASIC designs incorporate advanced in-situ testing capabilities, which are critical because high reliability is a prerequisite for automotive.”

Arsovski also mentioned that, since many GF clients vary in their design service requirements, the company offers a full range of packages from full-turnkey service – where the client delivers a spec and requires design center, packaging and test support from GF – to full custom design where the client delivers GDS and only wants fabrication. GF’s agility allows the company to organically support clients as their company and design capabilities grow in the field of automotive electronics.

About Author

Gary Dagastine

Gary Dagastine is a writer who has covered the semiconductor industry for EE Times, Electronics Weekly and many specialized media outlets. He is a contributing editor at Nanochip Fab Solutions magazine and also is the Director of Media Relations for the IEEE International Electron Devices Meeting (IEDM), the world’s most influential technology conference for semiconductors. He started in the industry at General Electric Co. where he provided communications support to GE’s power, analog and custom IC businesses. Gary is a graduate of Union College in Schenectady, New York,