By: Dave Lammers

Using GF’s 45RFSOI technology, UCSD Prof. Peter Asbeck recently developed a power amplifier operating at 28 GHz with output power of 22dBm and more than 40 percent power-added efficiency (PAE).  When backed off for the 64QAM OFDM signals used in 5G, the amplifier achieves an average output power of 13 dBm at 10 dB backoff, with 17 percent PAE, even without digital predistortion.“This is the right level of power and efficiency for the majority of the 5G 28 GHz applications,” Asbeck said.

Power amplifiers (PAs) are a different breed of cat from most other chips, and the PAs needed for the 5G wireless solutions are likely to be much different than those used in today’s 4G smart phones and base stations. Most 5G wireless applications will use phased array antennas to focus and steer multiple beams, and it is this ability to divide the transmission task among multiple beams, which gives 5G the ability to achieve what, to many, seem improbable performance targets.

While early 5G systems will use the sub-6 GHz frequency range, the real promise of 5G comes from using bandwidth in the 24, 28, and 39 GHz millimeter-wave ranges. There, phased array antennas, such as a 4×4 array, will be deployed, with each PA operating at much lower power than those needed to amplify the single-beam, omnidirectional signals used now.

Peter Asbeck, Professor at USC

Ned Cahoon, RF business development director at GF, said in the 4G wireless generation, gallium arsenide (GaAs) has been a leading technology in the power amplifier sector. “We believe we are moving from a sub-6-GHz regime, where gallium arsenide has dominated, to the millimeter-wave market, where most front-end solutions will be in silicon.”

Already pervasive in handset switches and antenna tuners, Cahoon said RF SOI technology – in production for over a decade and now extended by GF to 300mm diameter wafers at the 45nm node – is ideal for the integrated front-end devices needed for the millimeter-wave 5G handsets, access points, and base stations.

Cahoon bases that belief partly on work being done by several of the key professors working in the power amplifier field, notably Peter Asbeck at the University of California at San Diego (UCSD). Asbeck earned his doctorate at M.I.T., spent 15 years in industry developing high-frequency wireless technologies, and became the Skyworks Professor in High Performance Communications Devices and Circuits at UCSD’s Jacobs School of Engineering, and is a Member of the National Academy of Engineering for his development of the GaAs HBT device.

State of the Art

Using GF’s 45RFSOI technology, Asbeck recently developed power amplifiers operating at 28 GHz that can provide up to 22dBm output power and peak PAE of more than 40%. In a 5G application, the transmitted waveform requires substantial backoff from peak power, and excellent linearity.  The 45RFSOI circuit provides an average output power of 13 dBm, with 17 percent backoff PAE for the 5G case. “This is the right level of power and efficiency for the majority of the 5G 28 GHz applications,” Asbeck said, adding that the PA was used to transmit the standard 64 QAM OFDM signals, without using expensive digital pre-distortion (DPD) filtering techniques. While noting that other research labs are approaching similar results, he described his lab’s 45RFSOI-based power amplifier as “pretty much state-of-the-art.”

“There is really intense competition now between different technologies for the emerging 5G system slots.  45RFSOI is very close to being the ideal technology for configuring the RF front-end modules for 5G at 28 and 39 GHz. I think it is likely to emerge as the winner for very many 5G systems,” Asbeck said.

That statement is particularly interesting because during his career much of Asbeck’s work has been in gallium arsenide (GaAs), which is able to support the high voltages required for power amplifiers more easily. Since moving to UCSD in 1991, Asbeck has pioneered the ability to put silicon-based transistors in a series to achieve higher voltages, with these “stacked” transistors together providing the required output power. Four transistors in a serial arrangement are sufficient to produce the voltages required for most PA’s, he said. (Cahoon said, simply put, RF power equals the voltage times the current, with higher voltages needed for optimal linear circuits; basically the opposite of digital ICs.)

Asbeck is quick to note there are competing technologies to 45RFSOI, including gallium arsenide (GaAs), gallium nitride (GaN), and silicon germanium (SiGe). Another contender is the 22FDX® technology from GF. In a Foundry File blog last year, another professor at UCSD, Gabriel Rebeiz, described the work he is doing to develop low-noise amplifiers (LNAs) in the 22FDX technology.

Rebeiz, in an interview, said he believes the power levels in 22FDX-based amplifiers can be increased so that integrated 5G front-end solutions can be developed. But Rebeiz tipped his hat toward Asbeck’s work in 45RFSOI, saying “it is essential that the functions be integrated together, without that you do not have a (marketable) part. With RF SOI, besides the stacked-transistor PAs, you can also stack the switches. My group, together with GF, has shown 45RFSOI-based switches with only 0.8 dB of insertion loss. So yes, 45RFSOI is an ideal front-end-module technology.”

Besides the power amplifiers, RF front-end solutions need to integrate the low-noise amplifiers and switches, as well as phase shifters and variable gain amplifiers. RF SOI, Asbeck said, has proven to be “the world’s best approach” for millimeter-wave switches, which “outshine” switches available in SiGe HBT or GaAs technologies.

“There are some applications in 5G, to be sure, that require higher output power than has been demonstrated so far in 45RFSOI. The first generation 5G deployments may employ PAs in other technologies such as SiGe HBT or GaAs or GaN.  But we think there is a great opportunity to further increase the output power achievable with 45RFSOI into the Watt range for peak power, and to take over these slots as well as the lower-power ones,” he said.

Minimizing Parasitics

What gives RF SOI an edge? Asbeck said to reach the required levels of output power, transistor stacking “needs to be done – that is, placing a number of FETs in series, so that the overall voltage handling is increased.” The silicon-on-insulator structure of 45RFSOI removes all the parasitics associated with body-effect and substrate capacitance that hamper circuits made in bulk-CMOS.

Also, 45RFSOI has a high-resistivity substrate that “minimizes the capacitances of interconnects as well as of the devices. The three thick metal layers make the losses of matching networks the lowest of pretty much any IC technology. And the high Ft and Fmax values provide lots of gain at 28 GHz,” he said.

Battery life, so important in handsets, relates to the efficiency of the power amplifiers. Asbeck said, “45RFSOI ​has exceptional efficiency for the 28 GHz amplifiers, and it is pretty close to the best achieved in GaAs or GaN. I think that the high substrate resistivity and thick metals by themselves add about 5 percent to the PAE (power added efficiency) of the 28 GHz power amplifiers that we have made. Our record is 47 percent PAE, with saturated output power of 19.5 dBm in a simple 2-stack PA. A couple of other laboratories are reporting PAEs in this range too, using 45RFSOI.”

Cahoon said Asbeck’s 45RFSOI work has demonstrated the value of high-speed pFETs, along with the nFETs. Asbeck said the fast pFETs will enable the use of complementary circuits, with the pFETs improving the AM-PM characteristics of mostly nFET circuits. “We are also optimistic about mostly pFET circuits, because these transistors actually have potentially even better voltage handling than the nFETs,” he said. (The AM-PM conversion of an amplifier is a measure of the amount of undesired phase deviation (PM) that is caused by amplitude variations (AM) inherent in the system.)

For me, I took away two thoughts. One is that GF’s “pivot” away from leading-edge bulk CMOS in order to support technologies such as RF SOI was a smart move.

And listening to Asbeck, Cahoon and Rebeiz, one senses a confidence that millimeter-wave 5G wireless is readily achievable, providing the world with unbelievably fast wireless connections based on affordable, highly integrated ICs.

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.

By: Dave Lammers

With decades of development behind it, embedded STT-MRAM is coming to market, replacing embedded NOR flash, which has run out of steam at the post-28nm nodes due to power, mask-complexity, and bit-cell-scaling issues.

I’ve been to many IEDM conferences where companies went head-to-head in the logic arena; for example, Intel versus IBM in microprocessor logic. The 64th International Electron Devices Meeting, held in San Francisco in early December, was memory centric, as engineers from GLOBALFOUNDRIES and several other companies discussed their embedded MRAM programs at the IEDM podiums.

Just about all new technologies present themselves, and then face years of “crossing the chasm,” proving out reliability and gaining customer acceptance, said Tom Coughlin, president of data storage consultancy Coughlin Associates, referencing the 1991 book by Geoffrey Moore.

“Not depending on Moore’s Law scaling has liberated the industry,” Coughlin said. “We are getting away from the traditional ways that we build chips, turning to chiplets. And we can’t crank the traditional memories the way we used to.”

Embedded MRAM is a prime example of the industry’s creativity. With decades of development behind it, MRAM finally is coming to markets as a flash replacement technology. GF has a lead in the MRAM arena, said Kangho (Ken) Lee, the MRAM device lead at GF Singapore, as a result of the technology and manufacturing experience gained from a joint development agreement with STT-MRAM manufacturing partner, Everspin Technologies (Chandler, Ariz.).

Ready to Go

At IEDM in early December I met with Lee and his colleague, reliability engineer Lim Jia Hao, and asked: Is MRAM ready to go for NOR eFlash replacement?

“We have been doing production for Everspin, and that is absolutely helping. Our embedded MRAM is getting ready for production. We are qualifying our process now and this is going to be done soon. NOR flash replacement is very possible. Technologically there is no barrier,” Lee said.

In his IEDM presentation, entitled a “22-nm FD-SOI Embedded MRAM Technology for Low-Power Automotive-Grade-1 MCU Applications,” Lee detailed the work being done to meet the stringent requirements of the automotive market, where an embedded memory must be able to withstand operating temperatures as low as minus 40 degrees C and up to 150 degrees C.

“What we are talking about at this IEDM is our MRAM for automotive-grade applications. To date, no company has shown macro-level data at this temperature range, especially at 150 degrees C. We are showing the feasibility of an automotive MRAM, and that is very important to enable embedded STT-MRAM as a non-volatile-memory platform in the future,” Lee said.

In particular, the GF eMRAM showed a sub-ppm bit-error rate (BER) and superb reliability. “There are many MRAM applications and we have a technology platform that can serve many applications. ADAS (Advanced Driver-Assistance Systems) could be a very important one. One of the challenges is to get up to the 150 degrees C read margin. MRAM, because of its device properties, loses read margin at higher temperatures,” Lee said.

A Path Toward Automotive Qualification

Martin Mason, senior director of embedded memory, said GF is actively engaging with customers, working on new designs with embedded MRAM on the 22FDX® platform. Multiple production tape outs are scheduled for 2019.

The IoT and other low-power-centric designs will come first, followed by automotive-use SoCs in 2020. Mason said “a significant fraction” of GF’s existing customers are producing complex automotive-use microcontrollers. Mason said getting MRAM through the automotive qualification process is critical for GF and the automotive industry for their future product roadmaps.

“There are no  major blocks to prevent us from meeting the requirements of our automotive clients. We are talking to them about being qualified in the second half of 2020. We see a roadmap and a path to get there, and that’s what is important. We now have the (eMRAM) macros and are working with customers on new designs to characterize what we have at hand. Do we believe we can meet the specs? The simple answer is ‘yes, with a little engineering,’” Mason said.

Jim Handy, a memory analyst at Objective Analysis, said consumer devices, such as a heart monitor, rarely go much above a human’s body temperature. But an engine or transmission controller must operate in all kinds of temperatures, both high and low, which Handy said is “setting a hard goal” for eMRAM. But the customers need it; there is no NOR flash alternative past 28 nanometers.

“MRAM may be attractive at leading-edge nodes, not only for the high-complexity MCUs such as the engine and transmission controllers, but perhaps also for the entertainment system, which is not a life-and-death system,” Handy said, adding that most of the more than 100 MCUs in a modern car will continue to use NOR flash on somewhat older process nodes.

Saving EV Battery Power

Coughlin said as ADAS-enabled cars powered by batteries come to the market, carmakers are searching for high-complexity MCUs that do not consume a lot of power and can withstand high temperatures. “ADAS Level 4 is being targeted now, and that is a very complex system. With high transistor counts on those MCUs, companies need to put those designs on a leading-edge technology, and the eMRAM to support it is right on the doorstep,” Coughlin said, adding that “the biggest problem is that MRAM is new and the industry doesn’t have as much experience making it, especially for the higher temperatures.”

Mason said GF’s automotive customers need the 22FDX with eMRAM not only for engine and transmission control, but for other processors exposed to high temperatures. MCUs exposed to heat in the dashboard, in ADAS RF-Radar and LIDAR systems or in cameras mounted on front or rear car windscreens – all of which are exposed to demanding thermal conditions.

Different Interfaces, Side by Side

Mason described a capability unique to GF: putting a NOR-flash replacement eMRAM macro on a die with another, smaller eMRAM macro with an SRAM-type interface. These pre-built and verified eMRAM macros can be dropped into 22FDX designs. There are now 32- and 16- Mbit macros built with a single magnetic tunnel junction (MTJ) bit cell and a NOR flash-type interface with a 4-Mbit macro is planned for the first half of 2019. The 2-Mbit macro with an SRAM-like interface uses two MTJs for each bit cell to improve the read and write speeds.

Using the same underlying MTJs but with different sense amps, the flash-type macro has an interface for code storage, while the SRAM-type macro resides on the same chip for a persistent working class memory, providing a complete system within a microcontroller.

“A number of customers use both macros in their designs. Using MRAM doesn’t give much of a density savings compared with SRAM at 22nm, but they told us ‘that doesn’t matter, it is really about power.’ In many of these portable applications, power is what is critical. Clients really love to exploit the persistence for the power savings inside the chip, having the ability to be completely static, support fast start-up from power down and retain data values,” Mason said.

Handy, a memory designer early in his career, said for several decades people have written code for separate ROM and SRAM functions, in much different (flash and SRAM) transistors. “At some point people will get the brilliant idea to put the SRAM function in the MRAM, and then people will start changing the way they write their code. But people have become comfortable writing code the same way for three decades, and it will take time to fall into place,” he said.

Handy said the MRAM bit cell is fairly small if it is built in the lower metal layers with smaller pitches. There, MRAM can have roughly half the bit cell area compared with an SRAM cache, providing die size savings. But in the higher metal layers, the MRAM and SRAM sizes are similar.

Mason said GF is working with many customers, running multi-project wafers (MPWs) with eMRAM on 22FDX®-based designs. Embedded MRAM has passed multiple (five times) solder reflow tests, and exhibits extended data retention and endurance. It has “very comparable” read speed and much faster (order of magnitude) write speed (200 nanoseconds compared to 20 microseconds) than flash.

“Combined with the low-power back-biased SOI process and RF capabilities, GFs 22FDX platform makes for a highly differentiated IoT development technology,” Mason said, adding that “there is a critical industry pivot underway to new NVM memories and silicon on insulator technologies.”

Customers will be evaluating GF’s 22FDX process with MRAM for their next-generation IoT (MCU) designs to take advantage of these new technologies, he said.

“With eMRAM there are very few data retention concerns, unlike flash which has major problems there. We have a very extensive design win pipeline, with over 250 million dollars in design wins. We are getting ready for production, finalizing our qualification activities. Unlike other embedded MRAM solutions we designed it to be robust – we think that is key to adoption as a eFlash memory replacement and to ‘cross the chasm’ from early adoption to mainstream acceptance.”

“MRAM is going to happen, but right now it is crossing the chasm,” Coughlin said. When a new technology comes on to the market, “what generally happens is that we try a number of different markets to see where it will best work. That is what is happening now with MRAM. You start to build up your volumes and amortize costs. The whole game is getting the volumes up. The more costs come down the more it will be favorably seen,” he said.

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.

By: Dr. Thomas Caulfield

Dr. Thomas Caulfield, CEO, GLOBALFOUNDRIES

2018 has been a volatile year by almost any measure, and the global electronics industry was at the center of the action. Soaring memory prices and tech stock valuations drove eye-popping growth in the first half, with Samsung solidifying its position as the world’s largest chipmaker and Apple briefly topping $1 trillion of market capitalization. Fast forward to the second half of the year and we muddled through falling stock prices, fears of a looming trade war, and a GPU inventory glut.

The “crypto hangover” described by Nvidia CEO Jensen Huang is an apt metaphor: After a night of celebration, we woke up in a stupor—rubbing our eyes and struggling to comprehend our surroundings.

To help clear our heads, we need to step back and look at the bigger picture. When the ground feels unstable, it is often a sign of seismic activity below the surface. Our industry is in the midst of a tectonic shift from the age of mobile computing to a new phase of growth that will be driven by a range of emerging applications such as IoT, artificial intelligence, and 5G connectivity. The number of connected devices will explode into the trillions, which will drive equally explosive growth in data traffic across worldwide networks.

Each level of the electronics supply chain is striving to adapt to the challenges and opportunities presented by this coming era of “connected intelligence.” Systems builders are adapting by developing infrastructure and devices designed to manage, analyze and act on this data—both in the cloud and at the edge. Chip designers are shifting their focus from general-purpose computing to domain-specific computing, where a uniquely defined architecture can dramatically increase performance and reduce power for a highly specialized application such as machine learning. And manufacturers are adapting to the impending demise of Moore’s Law. It is no secret that transistor scaling—the engine that has fueled the industry for nearly 50 years—is running out of gas.

So how can silicon foundries adapt?

At its core, Moore’s Law is an economic model. It is about delivering increased capabilities at decreased cost. Like all useful business maxims, it hinges on the ability to provide value. In the semiconductor industry, we have trained ourselves to believe that value creation only comes through transistor scaling. But in fact there are many ways to achieve the net effect of Moore’s Law, and they do not all require billions of dollars in annual R&D and capital expenditures.

In a data-centric world, power efficiency is a fundamental metric. Power consumed per bit must be minimized to further enable data-rate growth within a constrained power envelope. As we approach the limits defined by physics, shrinking transistors is no longer the best way to reduce power. The transition to domain-specific architectures in the data center and at the edge opens up new architectural possibilities, which can be supported at the manufacturing level through new materials, transistor enhancements and advances in packaging.

At GLOBALFOUNDRIES, we have been altering our course to adapt to the realities of this new era. I have laid out the rationale for our recent strategy change in multiple forums, so I will not rehash it here. I encourage you to watch this video interview with Dan Hutcheson of VLSI Research for additional context. While there has been a great deal of attention on our decision to refocus investment away from the leading edge, this “pivot” was just one piece of a larger transformation that is underway at the company.

As we continue this transformation in 2019 and beyond, we will make significant investments in R&D to enhance our existing technology platforms with an array of differentiated features. By adding a feature such as high-voltage operation to a more mature node, it transforms from a commodity-like process to a true value-added technology for clients. This is nothing new—our fabs in Singapore have been operating this way for years, and they have great margins to show for it. We are going to replicate this model across our portfolio, including our most advanced technologies. Our development teams have already shown that, through a combination of architectural, memory and packaging innovations on our 12nm platform, they can deliver almost double the improvement in power consumption compared to traditional node migration.

But these differentiated features will not be developed in isolation. They can only deliver real value if they are designed in partnership with innovative clients who are positioned to take advantage of high-growth markets. We are forming deep partnerships with a new breed of clients, engaging at multiple levels from silicon to systems. Synaptics is a great example. They have adopted our 22FDX technology as the sole platform for their next-generation voice and multimedia processing products for the IoT market. Our teams have worked hand-in-hand to take advantage of the unique features of 22FDX, such as ultra-low power operation and unmatched RF performance. You can hear more from Synaptics CEO Rick Bergmann in this video of his keynote at our GTC 2018 conference earlier this year.

For GF to be truly relevant, we need more than differentiated offerings. Clients have made it clear that they need a foundry partner with a sustainable business model, so they can be sure their technology investments can generate returns for years to come. We have placed a new emphasis on financial performance and we will continue to accelerate this focus in 2019 and beyond. Our decision to shift investment away from the leading edge has freed up a tremendous amount of resources, and we will look for additional ways to improve our cost structure. Expect to see more changes to our technology portfolio as we double down on the most differentiated offerings, and anticipate refinements to our fab footprint as we look to optimize our capacity profile.

GF will celebrate its 10th anniversary in March of 2019. Much has changed in our business and the broader industry over the past decade, but one thing remains the same: semiconductors are critical components of the global technology revolution. In 2018, the semiconductor sector is estimated by some analysts to surpass $500 billion. While impressive, this number significantly underestimates our industry’s contribution to the $2 trillion electronics ecosystem. As we grapple with a rapidly changing market and fundamental shifts in enabling technologies, we must collectively commit to capturing more of the value we create to keep driving innovation into the future.

About Author

Dr. Thomas Caulfield

Dr. Thomas Caulfield is the Chief Executive Officer of GlobalFoundries. Prior to being named CEO, Tom was Senior Vice President and General Manager of the company’s leading-edge 300 mm semiconductor wafer manufacturing facility (Fab 8), located in Saratoga County, NY. Caulfield, who joined the company in May 2014, led the operations, expansion and ramp of semiconductor manufacturing production at Fab 8.

Caulfield brings a track record of results through an extensive career spanning engineering, management and global operational leadership with leading technology companies. Most recently, Caulfield served as president and chief operations officer (COO) at Soraa, the world’s leading developer of GaN on GaNTM (gallium nitride on gallium nitride) solid-state lighting technology. Prior to Soraa, Caulfield served as president and COO of Ausra, a leading provider of large-scale concentrated solar power solutions for electricity generation and industrial steam production. Before that, Caulfield served as executive vice president of sales, marketing and customer service at Novellus Systems, Inc.

Prior to that, Caulfield spent 17 years at IBM in a variety of senior leadership roles, ultimately serving as vice president of 300mm semiconductor operations for IBM’s Microelectronics Division, leading its state-of-the-art wafer fabrication operations in East Fishkill, NY.

By: Dave Lammers

Faced with a slowing down of traditional markets and Moore’s Law scaling, the semiconductor industry is working hard to reinvent itself, to figure out the needs of new markets such as artificial intelligence, autonomous vehicles, the Internet of Things, and others.

Perhaps the most intriguing of these is artificial intelligence, with compute paradigms that can differ markedly from traditional processor-memory approaches. “For a long time, pattern recognition and cognitive tasks such as recognizing and interpreting images, understanding spoken language, and automatic translation were weak points for computers,” said Damien Querlioz, a French researcher who spoke on “Emerging Device Technologies for Neuromorphic Computing” at the recent International Electron Devices Meeting in San Francisco.

Since about 2012, progress has been accelerating in AI, both during the training and inference stages, but power consumption is still a huge challenge when traditional compute architectures are used. Querlioz, a researcher based at the French national laboratory CNRS, gave a telling example: the famous game of Go played in 2016 between Google’s AlphaGo and Lee Sedol, a world champion at the game. Sedol’s brain consumed about 20 Watts during their contest, while AlphaGo required an estimated >250,000 Watts to keep its CPUs and GPUs humming.

While power improvements have been made since then at Google and elsewhere, the effort to come up with new, less power-hungry devices for neuromorphic computing is intensifying.

Ted Letavic, senior fellow for strategic marketing at GlobalFoundries, said he thinks about AI in stages, a timeline moving from ways to improve conventional compute technologies to radically new devices and architectures that consume much less power. All along the timeline advanced packaging will play a key role.

“AI is upon us now, and we can use existing technology and add derivatives, using DTCO (design technology co-optimization) to optimize down to the bit cell design level,” Letavic said. GF technologists are developing ways to reduce power and boost performance for the 14/12 nm FinFET platform, including dual work function SRAMs, faster and lower power multiply accumulate (MAC) elements, higher bandwidth access to SRAM, and others. The FD-SOI-based FDX processes also consume much less power, especially when back-biasing techniques are deployed. With these technologies in the designer’s toolkit, Letavic said customers can “redesign the elements inherent to AI with a much lower power envelope than if they went right to 7 nm.”

In parallel to these DTCO improvements are the research and development efforts underway throughout the world for embedded memory and in-memory compute solutions based on phase-change memory (PCM), resistive RAM (ReRAM), and spin-torque-transfer magnetic RAM (STT-MRAM), and FeFET. A PCM-based chip, developed at the IBM Almaden Research Center headed up by Jeff Welser, has demonstrated great progress, Querlioz said at the IEDM tutorial session, and STT-MRAM- and ReRAM-based AI processors also show great promise.   “We now have a huge potential to re-invent electronics for cognitive-type tasks and pattern recognition,” Querlioz said.

Letavic said the long-range need to reduce power consumption, especially for inference processing, is driving a host of startups to develop new AI solutions, and GF is working closely with several of them, as well as with long-time partners AMD and IBM.

“We can only get so far with DTCO improvements to von Neumann computing. The next step beyond disaggregated logic and memory is to move to compute-in-memory and analog-based computing,” Letavic said. Moreover, the instruction set architectures (ISAs) that have served the industry well for 35 years will need to be supplanted with new software stacks and algorithms. “When we go to domain specific compute, someone has to reinvent the software. IBM has some really good insights about the software stack,” he said.

“Everyone has to take this turn toward AI together. Foundries will go hand-in-hand with lead customers, and we can’t separate algorithms from the technology,” said Letavic, referring to this close cooperation at STCO, or system technology co-optimization. “STCO is a natural extension of DTCO as we move into the fourth era of computing. As we move to domain-specific compute that is a shift we will all take together.”

Packaging to Help Reduce Costs

While silicon advances – including dual work function metals in the gate stack, FD-SOI, and STT-MRAM – will improve performance, Letavic said packaging will play an equally large role, as companies move to link heterogenous devices made with the optimum process for each function. “I think after 20 years of discussion, 2.5D and 3D are going to be mainstream. We will see as much differentiation, if not more, from the packaging as you will from the silicon flows.”

Kevin Krewell, principal analyst at Tirias Research, said work being done with Advanced Micro Devices will give GF an advantage as companies put two or more chiplets in a single package. Earlier, AMD and Intel combined an AMD Radeon graphics processor with an Intel CPU in a single package. Now, AMD is boosting its Epyc server CPU line by using AMD’s Infinity Fabric interconnect technology. The forthcoming “Rome” server processor will feature multiple CPU and cache memory chip cores, linking those 7nm parts to a 14nm chiplet fabbed by GF that provides the I/O links to DRAM and the PCI bus.

By dividing tasks and using the optimum process for each function, chiplets connected over high-speed links will change how processors for several markets are created, Krewell said, noting that Nvidia, Intel and others are supporting high-speed chip-to-chip links.

“Using a mix of process nodes in a chiplet design, I do expect to see more of that. The I/O especially doesn’t scale well to 7 nm, and those functions take up a lot of space, even in 7nm. Sometimes it makes sense to put the I/O functions in an older chip. Historically, PC chip sets were made in an N minus 1 process, as part of a fab utilization strategy. Putting those functions in the right process node that can handle the I/O, where it is not as expensive per transistor, makes a lot of sense,” Krewell said.

Letavic said systems companies are demanding heterogenous integration using various forms of advanced packaging ranging from interposers, vertical through-silicon vias (TSVs), special laminates, fan-outs, and others. The strategy will also provide a boon to photonic connections, as opto-electronics can provide higher bit rates than some electrical connections can support.

Bob O’Donnell, principal analyst at market research firm TECHnalysis, said the chiplet strategy still has a ways to go before industry-wide standards are nailed down. Until then, companies such as AMD and others will use their own internal technologies to link multiple chiplets into SoCs.

“At a certain point, complexity becomes overwhelming and then companies start to look to simplify again. The problem is coming up with a fertile ecosystem among multiple vendors, allow packaging companies to package different parts from multiple companies. Those standards haven’t been nailed down yet.”

O’Donnell said the effort to use the optimum technology for each function is largely motivated by the high-cost of designing and fabbing large SoCs in a 7nm process, for example.

“The basic concept with chiplets, ironically, is that we are taking apart things that had been integrated in the past. The industry was able to integrate systems into fewer components, all the way down to SoCs that had almost everything in a single chip. But now, there is a slowdown because it is just so much harder from a technical perspective. The design costs at 7nm are extremely high, and the challenges from a manufacturing perspective are just crazy.”

Letavic said advanced packaging will provide benefits “at the chip level and at the system level. We are seeing it in the data center already. It is here to stay, and it will just get bigger.”

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.

By: Gary Dagastine

Whenever a company announces a major strategy shift and restructuring, as GF did in pivoting away from 7nm FinFET technology development, it’s understandable that confusion, uncertainty and misunderstandings may arise.

The best way to allay these concerns is to take an objective look at the situation: Demand for chips for the automotive, IoT, mobility and data center/wireless infrastructure markets is growing strongly. That opens up many new opportunities to leverage GF’s broad portfolio of existing, proven technologies by tailoring, or differentiating, them specifically for these markets. In addition, many potential clients in these areas are startups or non-traditional firms that can benefit from GF’s expanding service offerings. Stepping off the hugely expensive FinFET scaling treadmill, therefore, lets GF redeploy its resources to better pursue these opportunities.

Dr. Gary Patton, GF’s Chief Technology Officer and Senior Vice President of Worldwide Research and Development, explained these industry dynamics and discussed GF’s technology strategy in a keynote talk recently at the Global Semiconductor Alliance (GSA) Silicon Summit East 2018 forum in Saratoga Springs, NY. The Foundry Files sat down with him afterward to learn more.

FF: For decades progress in electronics has depended on making transistors smaller to increase the speed and processing power of integrated circuits. What has changed?

Gary: Scaling does still have a place for chips used in high-performance computing, but elsewhere the benefits to be gained by following Moore’s Law are diminishing as scaling costs escalate. That doesn’t mean innovation is finished, though. The good news is that existing technologies are now so powerful that by adding new features to them and combining them in various ways, new architectures and ways of computing are possible. What’s really happening is a shift is taking place, from a general-purpose computing approach to a more industry- or domain-specific one.

FF: How is GF taking advantage of this shift?

Gary: Very successfully, given that a majority of our revenue already comes from differentiated offerings. What we call the four pillars supporting everything we do are our FDX, FinFET, RF and power/analog-mixed-signal (AMS) technologies.

Our FDX technology is purpose-built for today’s power-sensitive applications, offering low active and standby power yet with the density and performance needed. It offers unmatched RF performance for always-on connectivity, low latency, and higher data rates to help make RF-driven IoT a reality. There is a lot of interest from clients designing chips for the IoT, especially as IoT will make a shift in coming years from WiFi- to RF-enabled. Overall we will have about 20 FDX production tapeouts this year, and we expect that number to more than double next year.

In FinFETs, we are realigning our roadmap to serve the next wave of clients that will adopt the technology in coming years. We have shifted development resources to make our 14/12nm FinFET platform more relevant to them by delivering a range of innovative IP and features. For example, for emerging enterprise, cloud and communication applications, we’re working on one-time and multi-time programmable (OTP/MTP) embedded non-volatile memory (eNVM) for ultra-high-security performance. This is based on GF’s physically undetectable and unclonable charge-trapping technology and will make possible market-leading security solutions. They also will offer higher levels of SoC integration. Our NVM solutions require no additional processing or masking steps, and are up to twice the density of similar OTP solutions based on dielectric fuse technology.

In RF, GF has a rich portfolio of offerings that align well with proposed architectures and which continue to advance in order to meet 5G and other requirements. RF FDX, for example, enables deep coverage, massive connections and low power consumption for narrow-band IoT, while RF FinFET technology offers excellent scaling and power consumption. RFSOI enables clients to build state-of-the-art LNAs/switches & control function integration for RF front-end modules, phased arrays, and millimeter-wave beamforming. Our various SiGe-based RF offerings are performance-tuned for a long list of low- and high-power applications including automotive radar/lidar, base stations, wired/optical/ mmWave & phased-array communications. By the way, clients are increasingly using our SiGe-based products with CMOS integration to displace the GaAs processes historically used for cellular and Wi-Fi power amplifiers.

Our AMS offerings span a wide range of process nodes (180-40nm) and voltages (3–700 volts), offering clients an outstanding selection of functions and price points. Our BCD/BCDLite and high-voltage (HV) technologies are based on GF’s efficient HV CMOS process and include power and HV transistors, precision analog passives and NVM memory for a wide range of traditional and emerging mobility, automotive, IoT and other applications.

FF: You mentioned in your talk that advanced packaging is a powerful differentiator for GF.  How so?

Gary: GF’s high-performance, cost-effective 2.5D, 3D, and silicon photonics advanced packaging technologies support each of the four pillars, and are aimed directly at emerging applications like 5G, networking/base stations, AI/ML and advanced automotive solutions.

For example, our though-silicon-via (TSV) technology is well-suited for differentiated uses such as TSVs for RF applications; grounded TSVs for power amplifiers; and isolated TSVs for stacking antennas and/or other passives on RF die (for excellent signal integrity and/or significant size reduction of mobile front-end modules). Also, when implemented through 2.5D and 3D die-stacking, TSVs can allow for reduced latency and power by moving memory closer to logic. Die-stacking can offer significant cost advantages through heterogeneous die partitioning and function re-use like splitting I/O, logic, and memory functions into smaller, lower-cost die using stacking package architectures versus traditional monolithic 2D design.

With regard to silicon photonics (SiPh) ICs, we have both fiber-attach and laser-attach packaging technology that will be offered through GF’s SiPh foundry offerings.

We have been executing qualifications of our advanced package offerings with major OSATs. For 3D packaging, we will support multiple thermal solution options at the OSATs depending on the product thermal needs, I would also like to point out that we have developed test technology for all of our advanced packaging solutions to help clients become familiar with them and speed their projects.

FF: What would you like to say about GF’s research activities now that the company has moved away from extremely scaled CMOS?

Gary: First of all, there was a perception that we were entirely focused on leading-edge research, or that it was the only research that really mattered to us, but that simply wasn’t the case. We have always conducted R&D to bring new features to our existing offerings, to add new capabilities, to increase their performance and/or to decrease their cost. Our FinFET technology provides a good example. First, we successfully integrated a MIM capacitor in the interconnect, which resulted in a 10% performance improvement. Then, we developed new IP libraries and achieved a further 5% boost. Right now we are enhancing the RF capabilities of these proven devices with an eye toward the rollout of 5G.

With the GF pivot, our research focus is to move more aggressively to differentiate our proven technologies—in effect, to create derivatives of them which enable new applications—to address the new opportunities we’ve been discussing.

FF: Where will this work take place?

Gary: We have a large R&D group in Malta whose focus is on differentiated CMOS technology development. Our team in East Fishkill works on silicon photonics, RF and packaging technology, key areas of differentiation for us. In Singapore we have a significant ongoing R&D effort in differentiated power and RF technologies at 40nm and larger nodes, while Burlington is where our industry-leading RF solutions are developed. We continue to collaborate with universities across the world and participate in industry research consortia such as imec, Fraunhofer and IME on a range of topics aligned with what we see as our best market opportunities.

FF: Any closing comments?

Gary: A company is only as good as its people, and I am very proud of our track record of first-time-right client tapeouts across our world-wide fabs. That’s not easy to do with such a complex set of technologies, and is a testament to the talent, professionalism and diligence of our colleagues and engineers.

About Author

Gary Dagastine

Gary Dagastine is a writer who has covered the semiconductor industry for EE Times, Electronics Weekly and many specialized media outlets. He is a contributing editor at Nanochip Fab Solutions magazine and also is the Director of Media Relations for the IEEE International Electron Devices Meeting (IEDM), the world’s most influential technology conference for semiconductors. He started in the industry at General Electric Co. where he provided communications support to GE’s power, analog and custom IC businesses. Gary is a graduate of Union College in Schenectady, New York.

By: Manuel Sellier

Fully depleted silicon-on-insulator (FD-SOI) relies on a very unique substrate whose layer thicknesses are controlled at the atomic scale. FD-SOI offers remarkable transistor performance in terms of power, performance, area and cost tradeoffs (PPAC), making it possible to cover from low-power to high-performance digital applications with a single technology platform. FD-SOI delivers numerous unique advantages including near-threshold supply capability, ultra-low sensitivity to radiation and very high intrinsic transistor speed, making it perhaps the fastest RF-CMOS technology on the market. On top of these advantages FD-SOI is the only CMOS technology to offer the possibility to fully control the threshold voltage of the transistors dynamically through body bias (Figure 1).

In order to explain why body bias is such a game changing feature we start with the problems it helps to solve. In the search for higher energy efficiency digital designers face two main challenges. The first one relates to the impact of variations, which modifies the actual chip specification defined by the extreme cases of variations (the so called “corners”). This tends to degrade significantly the energy efficiency of the chip (cf. Figure 2). Therefore, to optimize the energy efficiency, product engineers often use compensation techniques (cf. Figure 3). The most common compensation technique is based on Adaptive Voltage Scaling (AVS), i.e. playing with the level of supply voltage depending on the process centering of the chip. This technique is widely deployed in the mobile phone for process compensation but faces severe limitation in automotive and IoT markets because of the strong impact in terms of reliability, the difficulty to implement efficient temperature and aging compensation and the new and specific design know-how that it involves for most design companies.

The second problem lies in the optimization of energy consumption. With advanced technology scaling leakage power has most probably become the most critical problem to solve. It is important to balance correctly the level of leakage with the level of dynamic power. However, in bulk CMOS technologies the parameters fixing leakage (Vth, gate length) are mostly static and defined by process. There is therefore no adaptive leakage optimization possibility, except by switching off entire parts of the circuit. The energy point, i.e. the balance between dynamic and leakage power is fixed and cannot be changed dynamically.

Through its control of transistor threshold voltage, body bias acts as a control knob capable of solving most of these aforementioned issues facing designers targeting energy efficiency.

Not only can global variations be very efficiently mitigated, but also and most importantly, designers can design their chips with reduced design corners for process, temperature and aging, and boosting the Power-Performance-Area (PPA) tradeoff starting at synthesis.

The leakage, which is exponentially dependent on the threshold voltage, can now be modified dynamically with body bias. Energy optimization can be performed dynamically by simultaneously playing with the right amount of supply voltage and body bias. The resulting energy efficiency gain is double at nominal Vdd and can increase to 6x at ultra-low voltage.

To efficiently implement body bias at the circuit level, one must modify current power management infrastructure, which leverages today’s supply voltage only, to support power management solutions capable of managing both supply voltage and body bias.

Dolphin Integration has been cooperating with GF over the past two years to release the world’s first power management IP platform. This power management IP platform, now proven in 22FDX, consists in a consistent set of configurable Voltage Regulators, scalable and module Power Management Unit (a.k.a. PMU logic/ACU), Power IO and island Gating and Voltage Monitors.

To allow SoC designers to extract the full PPAC potential of FD-SOI for their SoC, the companies are now exploring the extension of this power management IP platform to enable the dynamic control of power supply and body bias. This extended power management IP platform will leverage existing body biasing solutions while complementing them with application-optimized body bias generators and advanced monitoring techniques (cf. Figure 5).

The presence of these kinds of solutions available on the market is driving the value proposition for FD-SOI outperforming PPA against any other technology for low power and energy efficient applications. More importantly, the availability of a body biasing turnkey solution lowers significantly entry barriers, making this FD-SOI value proposition available to all players, from mobile and IoT to automotive.

The value of FD-SOI is truly based on the capability to leverage body bias, which is a completely disruptive approach in the advanced CMOS landscape compared to existing technologies. FD-SOI is a game-changer, realizing an order of magnitude power efficiency gain. With the support of silicon IP providers like Dolphin Integration, new power/performance/reliability management infrastructures will be available to customers to fully leverage the benefits of this technology, paving the way to future performance standards in IoT and automotive.

About Author

Manuel Sellier

Manuel Sellier is Soitec’s product marketing manager, responsible for defining the business plans, marketing strategies, and design specifications for the fully depleted silicon-on-insulator (FD-SOI), photonics-SOI, and imager-SOI product lines. Before joining Soitec, he worked for STMicroelectronics, initially as a digital designer covering advanced signoff solutions for high-performance application processors. He earned his Ph.D. degree in the modeling and circuit simulation of advanced metal–oxide–semiconductor transistors (FD-SOI and fin field-effect transistors). He holds several patents in various fields of engineering and has published a wide variety of papers in journals and at international conferences.

By: Manuel Sellier

There is a consensus that “bleeding edge” technologies, i.e. the continuation of Moore’s law whatever the cost of the technology, is bringing less and less return on investment for most players in the semiconductor industry. In this context there is a critical need for more innovations beyond traditional CMOS scaling. There are many opportunities for innovation in the value chain from semiconductor materials and devices to services, but the simplest one starts with substrates.

RF SOI and FD-SOI are great examples of how the industry is pushing differentiation with substrates to develop new standards for RF communication and low power computing. GLOBALFOUNDRIES has been a successful pioneer in this strategy. First, RF SOI has become the de-facto technology for a large number of components of the Front End Module (FEM) in cellular phones. From almost nothing 10 years ago, today the total market for RF SOI is around 1.5 million wafers (8 inch equivalent). Second, FD-SOI is now the technology of choice for mmWave RF-CMOS connectivity and battery powered devices requiring a very high level of energy efficiency. We will review, in this post, how Soitec is supporting GF with outstanding RF SOI substrate solutions.

How SOITEC supports GF with differentiated RF SOI technology

5G will rapidly change the way people and objects around the world communicate; GF and Soitec are supporting this change providing innovative technologies that support the evolution towards 5G and its coexistence with other existent and future standards.

Different communicating devices (vehicles, smartphones, “things”) RF Front Ends require differentiated technologies that could offer the right cost/performance trade-off facilitating their introduction and adoption. Soitec offers two families of RF SOI substrates: HR-SOI using a high resistivity base substrate and RF Enhanced Signal Integrity TM (RFeSI) SOI which adds a trap rich layer on top of the high resistivity base helping deliver on stringent linearity requirements – both of which are compatible with standard CMOS processes and foundries.

These two families of substrates are available in 200 and 300 mm diameters and offer different advantages in terms of linearity, insertion loss, isolation, noise figure and other key specifications and therefore can be used to design and manufacture different blocks and functions in the RF Front End. The examples here below are given as reference only as integration strategy differs largely among different RF Front End solutions providers.

• Antenna tuners, which require very high linearity are typically implemented on RFeSI substrates
• Receiver/ Transmitter switches requiring good linearity, low insertion loss, high isolation and high integration level can be manufactured on HR-SOI and/or RFeSI substrates
• Low noise amplifiers (LNA) on the receive path typically implemented in technology nodes below 90nmare commonly manufactured on 300 mm HR SOI wafers and if integrated with switches and other supporting blocks in 300 mm RFeSI ones.
• Power amplifiers could be fully integrated in 300 mm RFeSi substrates with switches and LNAs for connectivity, IoT and 3G/early 4G cellular applications

Thanks to a long-term strategic partnership GF and Soitec have been timely delivering products tailored to address the needs of a very demanding RF Front End market in continuous evolution.  This partnership extends in many fields including engineering and manufacturing, securing state of the art performance in high volume production.

Soitec is integrated into GF’s roadmap thanks to a shared vision of the market evolution. In the most recent example, GF’s next generation mobile and 5G RF Front End 8SW technology was designed to fully exploit the benefits offered by Soitec’s products.

In a semiconductor world where everybody is looking for differentiation, RF SOI and FD-SOI represent unique platforms delivering major advantages. RF SOI value is now fully recognized. It has been adopted by most of the players in the cellular FEM business. It will see continued growth with the increased complexity of radios at 4 and 5G. Soitec is committed to serve this industry with the right level of capacity and quality.

In our next post we will review how Soitec is supporting GF with outstanding FD-SOI substrate solutions.

About Author

Manuel Sellier

Manuel Sellier is Soitec’s product marketing manager, responsible for defining the business plans, marketing strategies, and design specifications for the fully depleted silicon-on-insulator (FD-SOI), photonics-SOI, and imager-SOI product lines. Before joining Soitec, he worked for STMicroelectronics, initially as a digital designer covering advanced signoff solutions for high-performance application processors. He earned his Ph.D. degree in the modeling and circuit simulation of advanced metal–oxide–semiconductor transistors (FD-SOI and fin field-effect transistors). He holds several patents in various fields of engineering and has published a wide variety of papers in journals and at international conferences.