By: Dave Lammers

The last couple of blogs I’ve written have looked at using the 22FDX® technology process for Internet of Things and automotive radar applications, markets that call for a combination of performance at low power consumption. Cryptocurrency mining is another market where power consumption is a defining characteristic, one reason that miners are moving gradually away from GPUs to ASICs.

One of the interesting things about the semiconductor industry is that every application needs a different mix of performance, power consumption, cost, and other factors. The cryptocurrency mining applications are that way, even down to the major coins — Bitcoin, Litecoin, and Ethereum — and the ways they are mined.

Anshel Sag, an associate analyst at Moor Insights & Strategy, who tracks the coin mining market, said miners “don’t want to buy any extra logic on-chip. They want to minimize power. Everything is extremely lean because most of this boils down to power consumption.”

Each of the different algorithms, Sag said, presents “a different bottleneck, and the ASICs need to be architected in different ways to minimize the bottlenecks.” (Sag and Moor principal analyst Patrick Moorhead wrote a white paper on fabs and cryptocurrency miners that provides details on the subject.)

“With so much energy consumed daily, mining operations and manufacturers are always looking at the efficiency of their ASIC miners. Most mining devices ‘performance’ is measured in hashes per watt rather than total hashing capability.” Source: Moor Insights & Strategy White Paper, “The Importance Of Fabs In Crypto Mining”

Architectures Differ

Sanjay Charagulla, senior director of technology marketing and business development at GF, outlined the differences in the miner ASICs optimized for Bitcoin, Litecoin, and Ethereum. The Litecoin ASICs tend to have a relatively small fraction of logic transistors, while SRAM cells account for roughly two-thirds of the transistors. Charagulla argued that GLOBALFOUNDRIES’ 22FDX process has “one of the most efficient SRAM bit cells,” and cited that as a reason why GF has “already taped out multiple customer designs.”

Ethereum mining, which accounts for roughly 10 percent of the total mining IC market, thus far has been dominated by graphics processors (GPUs). The Ethereum algorithm requires a relatively large amount of external memory, and the die sizes are larger. Charagulla said he sees Ethereum mining growing to as much as a quarter of the market, because its overall commercial technology offers good transaction flexibility over Bitcoin.

With Bitcoin – still the dominant cryptocurrency despite a flood of new entries – the mining appliances typically have multiple PCB boards, with each board holding on the order of 50-100+ ASICs. These tiny ASICs are logic devices, with hundreds of multiply and accumulate (MAC) circuits on each die, requiring no external memories or co-processors. And if a couple of cores are not working, the ASIC is able to still grind away. “The Bitcoin ASICs are not that complex. The layout and back end design are key to efficiency,” he said.

With the cost of power so important to miners, efficiency is measured in milliWatts per gigahash, rather than total hashing capability. Bitmain, the dominant mining vendor, has described a 98 milliwatts per gigahash Bitcoin miner, and new competitors are seeking to either match or improve on that. “We have multiple customers engaged, and a handful already taped out, with good results,” Charagulla said.

Good Enough Performance

I asked Charagulla if miners could get to the next space on the blockchain faster by jacking up the ASIC’s frequency and paying for the extra power consumption. He replied that to keep the thermal flow within the miner at an optimum level and conserve power, the smart strategy is to run the ASICs at a “reasonable frequency of 400-500 MHz at the lowest power.”

Even though some Bitcoin ASICs are shifting to FinFET-based processes, Charagulla argued that the better strategy is to keep the manufacturing costs and power consumption down by using the FD-SOI-based FDX process, while maintaining sufficient performance. “The way to do this is to run thousands of cores in parallel, at a certain frequency, so they can still solve the puzzle. The cores are basically a bunch of XOR gates with a 16-bit-wide datapath, in a confined layout. Our belief is that 22FDX will meet the requirements here. Where FinFETs shine is at gigahertz clock speeds, with wider buses and bit-adder logic. In this case (Bitcoin ASICs) there is not any high-speed I/O, so if you can optimize the layout of the cores, FD-SOI can be as good as FinFETs, and at lower costs.”

Many customer designs using the FDX process operate at just 0.4V. Charagulla said one tier one customer is pushing down to a 0.3 Vdd to provide miners with a lower-power-consumption ASIC at 80 milliwatts per gigahash, while “still able to run the algorithm efficiently.” Back biasing and forward biasing can be used to meet the performance and power specs, he added.

Capacity Constraints

Sag, the Moor Insights analyst, said while some “premium” ASIC miners will continue to be made at leading-edge FinFET processes, other miners may take a different tack. “FinFETs on the more-expensive nodes provide higher performance, but at a cost. When the mining ASICs go to smaller design rules, the wafers are more expensive. Right now, people want to drive down the cost of miners, so they can sell more at a lower cost and get more profit. By being on a leading-edge node, such as 10nm or 7nm, the yields are not the greatest initially. The costs are high on a leading-edge node.”

Moreover, mining companies are “jockeying for fab capacity, another reason why the costs are higher,” Sag said.

With GF’s Malta, N.Y. fab running at nearly full capacity at 14nm and the upcoming 7nm processes based on FinFETs, Sag said the mining companies see available 22FDX capacity at Dresden as an opportunity. Moreover, with more than a half-dozen miner device manufacturers based in China, Sag said “22FDX could be used in China relatively soon.”

Sag noted that “GF is doing a good job of choosing the right processes for the right customers, for what is important to them. Not every chip needs billions of FinFET transistors. 22FDX makes sense in terms of price sensitivity, as well as the need for high efficiency.”

The Moor Insights white paper noted that the “GLOBALFOUNDRIES’ FDX roadmap will expand in 2019 and 2020 to include 12nm FDX, which should operate at even lower power and higher performance while also having a cost-friendly profile. We believe this product expansion could significantly benefit miners. The cost of manufacturing chips is becoming an increasingly important factor in their success, particularly as Bitcoin and other altcoin ASIC mining companies aim to turn as much volume as possible.”

Charagulla said the available capacity at Dresden is drawing new miner companies to 22FDX. “Malta is mostly full, and the Dresden fab is clearly positioned for 22FDX, and 12FDX going forward. We are getting design wins in millimeter wave RF, for base stations and mobile handsets and millimeter-wave radar. For the miner ASICs, FDX adds value, and that is why the new entrants are coming to us.”

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.

By: Yafeng Zhang

The booming automotive and IoT markets are driving increasing demand for microcontrollers (MCUs). Recent forecasts project that the overall MCU compound annual growth rate (CAGR) will reach 4% over the next five years, and in particular the automotive MCU CAGR could reach close to 14%.

Non-volatile memory (NVM) is a critical element of MCUs, as it is needed not only to store the code, but also to store the operating data throughout the product lifetime.

Two NVM solutions

There are two NVM solutions commonly used to build MCUs: NVM directly embedded in the system-on-chip (SoC) or a separate, external NVM chip assembled with a logic chip as a system-in-package (SiP) solution. MCUs with embedded NVM (eNVM) are fabricated in a special logic process that includes eNVM, and everything needed for MCU operation is created within that single chip. For MCUs that use a SiP solution, a NOR Flash chip and a logic chip are packaged together. Code and data are therefore stored off the logic chip on a standalone NOR Flash chip.

Top MCU providers primarily use an eNVM solution in their products, but a SiP solution may be an attractive option for smaller companies. Those companies may realize a shorter time to market, partly because using a standard, readily-available logic process may simplify and shorten the design cycle. However, a SiP solution may not meet all the requirements of many IoT and automotive applications. Using eNVM will often be the superior solution given the the cost, power, speed, security, stability, and reliability requirements of high growth MCU applications.

Choosing the best solution

To choose the best solution for an application, consider the following comparison of these two solutions based on key end market requirements of power consumption, power-up time, speed, security, reliability and cost:

• Power Consumption: eNVM offers more than 30% lower active power consumption than SiP because SiP flash requires constant IO toggle. Therefore, GF recommends eNVM for battery powered IoT applications that require low power. GF and eVaderis are co-developing a low power MCU using 22FDX and eMRAM
• Power-up Time: eNVM offers a 20x faster time to power up and access first data than SiP (5µs vs. 100µs) because eNVM is XIP, whereas with SiP flash, the system needs to copy the data to on-chip SRAM. Therefore, for normally-off applications that require very fast power-up and read times, GF recommends embedded eNVM.
• Speed: eNVM offers a 2x faster read speed than SiP (400MB/sec vs. 200MB/sec), since the eNVM macros have x32 to x128 bit IO bus width, whereas the SiP uses x4 or x8 bit Therefore, GF recommends eNVM for high speed/high bandwidth applications.
• Security: eNVM offers higher security than SiP because the eNVM macro can be customized and the SoC can use IP such as PUF to enhance security. In contrast, SiP flash is a standard offering in the market, and extra security cannot be added. So, GF recommends eNVM for high security applications.
• Reliability: eNVM offers higher reliability because it is qualified as a single SoC by the required reliability level, whereas SiP flash can only achieve high reliability by adding strict test screening on known good die (KGD) and the package. CMOS Embedded STT-MRAM arrays in 2x nm Modes for GP-MCU applications
• Cost: To compare the cost of the two solutions, several factors must be taken into account:
  • NVM memory density and full chip size, which determines the Gross-Die-Per-Wafer with or without eNVM
  • Wafer price, with or without eNVM
  • Extra on-chip SRAM density for SiP solution, which is used to download the code from external Flash during power up
  • Flash KGD price for SiP solution
  • Wafer testing cost, with or without eNVM
  • Additional factors like wafer yield, with or without eNVM, SiP solution FT yield loss, management cost

Comparing cost

The following cost comparison includes six typical NVM memory densities (2Mb, 4Mb, 8Mb, 16Mb, 32Mb, 128Mb) implemented both on GF’s 40nm LPx platform with eFlash, and also on the 22FDX® (22nm FD-SOI) platform with eMRAM.

Because every company has a different power up methodology for SiP solutions, various on-chip SRAM densities are used to “shadow” the external Flash. The following results assume the ideal case for SiP, where a SiP solution and eNVM solution utilize an identical SRAM size. Note that most common SiP solutions increase the SRAM size for code shadowing from the external Flash.

Source: GLOBALFOUNDRIES, 2018

The graph above shows that the 40nm platform with eNVM (eFlash) is lower cost when the NVM density is less than 16Mb, while the SiP solution is lower cost when the NVM density is equal to, or higher than 16Mb.

For a design utilizing 22nm FDX platform, the eNVM solution (eMRAM) is lower cost when the NVM density is less than 32Mb, while the SiP solution is lower cost when the NVM density is equal to or higher than 32Mb.

Comparing the two platforms, the 22FDX eNVM solution (eMRAM) has lower cost at all the NVM densities versus the 40nm SiP solution. In addition, for the 22nm platform the additional cost for eMRAM at higher densities (32Mb+) is 4% or less, while also outperforming a SiP solution in power, speed, security, and reliability.

For even larger SRAM densities, the advantages of an eNVM solution are even greater.

So, which solution is best for my MCU?

In summary, both eNVM and SiP solutions are viable methods to combine logic and NVM. However, eNVM is often a better choice for MCUs based on the superior power, speed, security and reliability. With respect to cost, eNVM is often a lower cost than SiP, especially below 32Mb NVM densities. As MCU makers consider all the trade-offs for their products, GF stands ready to assist clients in selecting the appropriate solution to win in their market.

In a recent Tech Talk video GF talks about the pros and cons of embedded non-volatile memory versus system in package.

GF offers a wide range of eNVM and SiP solutions using leading-edge and mainstream technology platforms from 130nm to 22nm to meet the diverse needs of emerging markets. The low power consumption of the cell core eMRAM series is ideal for the MCU and IoT markets, with ultra-fast access speeds and high storage capacity making it the perfect companion for the computing and storage markets. eFlash solutions (plus RF and analog modules and a variety of IP) are optimized for specific applications such as wearables, IoT, automotive, industrial and consumer electronics.  GF SiP solutions offer fast time-to-market with proven technology.

Please contact GF for a precise comparison of SiP vs. eNVM for your specific MCU architecture.

About Author

Yafeng Zhang

Yafeng has about 15 years of experience in the semiconductor industry, with expertise in design, application and technical marketing of NOR flash. Yafeng drives the technical marketing of the eFlash product offerings from 130nm to 40nm, with particular focus on the automotive and industrial MCU customers.

Before joining GF, Yafeng had the senior engineering roles, most recently at Micron Semiconductor where he focused on 45nm NOR flash design and products application. Prior to that, Yafeng held various positions at Synopsys and SMIC.

Yafeng holds a Master of Engineering degree in Micro Electronics, and a Bachelor’s degree in Materials Science from Fudan University, Shanghai, China.

By: Dave Lammers

“There are far fewer bigots out there than there were two years ago.” Dan Hutcheson, CEO of VLSI Research

Two years ago, when Dan Hutcheson, CEO of market research firm VLSI Research Inc. (Santa Clara, Calif.), set out to interview influential IC and intellectual property managers about fully depleted silicon on insulator (FD-SOI), he found two top-of-mind concerns: the availability of external IP which design teams could combine with internal intellectual property, and the then-lack of a process technology roadmap.

Hutcheson redid the VLSI Research survey this year and found a different landscape: the 2018 survey respondents were much less concerned with the roadmap issue now that GLOBALFOUNDRIES has committed to a 12nm node for its FDX technology, and “IP is much less of an issue,” Hutcheson said during a presentation of the 2018 survey results at the 2018 SOI Silicon Valley Symposium in late April.

Hutcheson asked 24 people—decision-makers at companies accounting for more than half of the IC and intellectual property markets—about  the transistor reasons to design with FD-SOI. Nearly 40 percent cited “better gain for analog” as the top reason, with a similar number citing lower leakage and better parasitics. Lower noise, better transistor matching, thermal properties, reliability concerns, and better radiation protection followed in importance.

The 2018 survey participants are now aware that RF and mixed-signal technologies are more readily implemented in FD-SOI, including a widely held view that FD-SOI is a better solution for 5G and millimeter-wave RF SoCs.

Times Have Changed

When the 2016 survey was conducted, finFET-based processes were just becoming available. At that time people were thinking in either-or mode: either finFETs or FD-SOI, one or the other. Now that finFETs have become widely available, more nuanced thinking is taking hold. “Now, most people have said finFETs and FD-SOI are complementary technologies, and which one you use depends on application needs,” Hutcheson said.

FinFET-based technologies offer higher performance, integration, and density. However, the design and mask costs are higher than FD-SOI, even though finFET costs have come down over the last two years due to depreciation of tool sets.

Many of the survey respondents said the primary advantages of FD-SOI centered on RF, or “high-mix SoCs” with analog, digital, and RF on the same die. In product markets where RF and sensor integration are valuable, FD-SOI is seen as the way to go “much more than before,” he said.

The respondents told Hutcheson that the fully depleted planar transistors on SOI offer “better gain for analog, better matching, and they are much easier to match. The automotive guys see a better thermal range, and more stable operation” in automotive environments. Also, analog designs benefit from the better gain possible with the FD-SOI depletion-mode transistors, compared with the enhancement-mode transistors of finFETs.

“FD-SOI is uniquely positioned for 5G because of the better parasitics. Some people are trying to use fins for 5G, but fin parasitics are a deciding factor. To paraphrase the respondents, ‘You can always find a way to engineer around anything. But the question is: How much do you want to pay to engineer around that?’” he said.

The 2018 survey asked for the top reasons to favor finFETs. The largest reasons were the performance and density advantages held by leading-edge finFETs. Nearly 30 percent said “FD is not cost-effective on a structural basis in these domains.”  About 15 percent of the respondents said they believe millimeter-wave ICs are “possible to do with bulk.” Others cited a wide variety of reasons for preferring finFETs, including challenges in designing with back-biasing, the finFET ecosystem “has no peers,” a lack of FD-SOI IP, and “management says no.”

“I asked about body-biasing and found people who said it was oversold,” Hutcheson said. One person said “if I go to my boss and say, we ought to do this because we want to do body-biasing, he is likely to say it is too complex and risky, so just do bulk. It’s better to first sell them on FD’s unique transistor features to management first and then add body-biasing as a bonus later.”

The respondents said FD-SOI had business-reason attractiveness, with about 30 percent citing lower design costs as the top business reason to design with FD-SOI. Lower manufacturing costs, fewer masks, and faster cycle-times/ time-to-market followed.

Hutcheson noted that the Internet of Things label encompasses several large market segments. For edge IoT markets where power consumption is important—which he referred to as “clever power with on/off mission profiles” —FD-SOI “has a huge advantage.” And, he said the survey indicated FD-SOI has advantages for markets where the product life is short, and for companies that have ”low budgets for chip design.”

The main takeaway from the 2018 survey is that managers and engineers are more willing to consider FD-SOI as a complement to finFETs, or in some cases as the only process roadmap that fits their company’s product requirements. Fully 75 percent of the survey respondents said they would consider running two roadmaps, one for finFETs and another for FD-SOI.

“Two years ago, people had a dramatic take on the question: is it finFETs? Or is it FD-SOI? At that time it was an OR-gate kind of situation, but now it is more like an AND gate. People are willing to use both. There are far fewer bigots out there than there were two years ago,” he said.

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.

By: Dave Lammers

High resolution imaging radar enables cars to sense the environment in all weather and lighting conditions to long, mid and short ranges as well as in any azimuth, elevation, and Doppler. It tracks velocity, and detects distance better than sensors now on the market.

The two recent incidents related to self-driving cars in the United States demonstrate the urgent need for improved sensors and related ADAS (Advanced Driver Assistance Systems) technologies. Arbe Robotics, a startup with roots in Israeli military radar technology development, is among the companies answering that need, as it begins rolling out a high-resolution automotive imaging radar chipset based on the 22FDX® technology from GLOBALFOUNDRIES.

Arbe Robotics’ imaging radar provides a high resolution of 1° azimuth and 1.25° elevation, at distances exceeding 300 meters and at a wide field-of-view of 100°.  The company said its advanced technology allows the detection of small targets, such as a human or a bike even if they are somewhat masked by a large object such as a truck. The imaging radar can determine whether objects are moving, and in what direction, and alert the car in real-time about a risk.

While other car sensors can fail when it is raining, if there’s fog, and due to blinding lights such as a sudden reflection. Arbe’s radar is completely oblivious to all those factors. The custom designed radar processor creates a full real-time 4D image of the environment, and classifies targets using their radar signature.

“The performance we can show leapfrogs the existing radars,” said Avi Bauer, vice president of research and development at the Tel Aviv-based company, founded in 2015. In a previous role he benchmarked the available process technologies – ranging from silicon germanium (SiGe) to bulk CMOS – and found them all lacking. The fully-depleted SOI technology of 22FDX met the needs of both the radar front-end device and the processor. Having both chips made on 22FDX will make it easier to combine them into a single-chip solution as the company’s next-generation offering.

Bauer said that at his previous job, “we hit the glass ceiling with respect to efficiency due to the limitations of bulk CMOS,” including power handling. Bauer said that CMOS, at 28nm design rules, falls short both on integration and long-range radar power. Silicon germanium – used today for long-range radar – performs well but is power hungry and has low density. Moving to a largely digital RF design on a 16nm FinFET process would be too expensive and risky.

“With SOI the design is more straightforward, and (voltage) biasing allows you to do things that cannot be done in standard CMOS,” Bauer said. For the transmit and receive modules, SOI’s higher resistivity substrate benefits the passive components – inductors and capacitors – and allows good isolation. “High Q passives are important. At 22nm, SOI allows better performance overall.”

By avoiding the high mask counts and expensive design tools required for FinFET-based designs, Bauer said the 22FDX process meets the company’s power, performance, and density objectives, while remaining on a Moore’s Law cost-per-function curve. Speed and transistor density are important: high-resolution imaging radars generate enormous amounts of data, which must be processed close to where the sensing is happening, at very low latencies. Arbe developed a custom processor for the radar data analysis, Bauer said, and uses an off-the-shelf processor for memory and other control functions.

To LiDAR, or Not

Bert Fransis, a senior director at GF, said that with a high-resolution imaging radar system which can “see” under all weather conditions, ADAS vehicles “would have something of a winner compared to LiDAR.” Fransis said he believes that high-resolution imaging radar eventually will largely supplant deployment of LiDAR (Light Detection And Ranging), the laser-based sensors often seen on the top of today’s ADAS test cars. The ADAS companies could combine CMOS image cameras and high-resolution imaging radar and “significantly cost reduce what a vision system for a car would look like.” The rotating LiDAR modules mounted on the roofs of test cars cost $10,000 or more, and only work well on a clear day, and even then at relatively meager 20 Hz frame rates.

Today’s LiDAR modules “don’t work in foggy, snowy weather. They only provide high resolution under severe constraints,” Fransis said.

Phil Amsrud, senior analyst for automotive electronics and semiconductors at IHS Markit, said there are innovations going on in the LiDAR arena, ranging from MEMS-based and all-solid-state LiDAR, which are likely to keep LiDAR in the “sensor fusion” packages of many car companies. “Looking at the data we have now, LiDAR is going to have a much longer life than just as a science experiment on test vehicles. There is so much effort going into new technologies with fewer moving parts, so many partnerships underway, that we believe LiDAR will be used in production-intent vehicles. It still fits into the sensor fusion mentality, and I see all of these technologies running in parallel.”

3D Plus Velocity Equals 4D

LiDAR may well continue to be deployed by certain car companies, even as Arbe Robotics and other companies push radar’s effective distance to the 300-meter-plus range, and to higher resolution imaging. It claims to be the first radar company to provide high-resolution 4D pictures (3D + Velocity), at a wide dynamic range for real-time obstacle detection.

Shlomit Hacohen, vice president of marketing at Arbe Robotics, said the company is providing prototypes to customers now, and will move to general availability by early next year. “Our imaging radar is a true enabler of road safety, as it works in all weather and lighting conditions. It tracks velocity, and detects distance better than any other sensor in the market,” she said.

Today’s radars support safety systems, including adaptive cruise control, blind spot detection, and automated emergency braking. “However, with the current radars on the market you need to trade off resolution and field of view,” Hacohen said.

The Arbe Robotics systems can be configured for rear, side, or front-view detection. The company touts its ultra-high resolution of 1° azimuth, 1.25° elevation, and Doppler resolution of 0.1 m/s. It supports a wide field of view of 100° azimuth, 30° elevation, and a real-time-refresh rate of 40 FPS (frames per second).

The company has patented its post processing technology, which reduces power consumption by pointing the camera and LiDAR only to the areas of interest.

MRAM Under Consideration

I asked Bauer if Arbe Robotics plans to use the eMRAM (embedded magnetic RAM) technology developed by GF, and he said it is under consideration for Arbe Robotics’ next-generation, single-chip design. “As a stand-alone system in single device, we probably need to take a look at eMRAM. Today, we are already on the edge, and adding another feature like eMRAM would add risk. But we are looking seriously at it for the next generation.”

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.

By: Mark Granger

Gone are the days when automotive electronics was a slow-moving, trailing-edge business. Today, powerful semiconductor technologies are driving the development of automotive features that once might have been seen as science fiction, such as advanced driver-assistance systems (ADAS) which are paving the way to self-driving cars.

Overall, the market for semiconductors in automotive applications is projected to see a 7% compound annual growth rate (CAGR) from now to 2023, from $35 billion to $54 billion. The ADAS applications where GF offers unique solutions, however, are projected to grow at a whopping 19% CAGR in that period.

The breadth of our technologies, systems design expertise, engineering resources and quality systems all put us in a great position to serve this growing market and provide the automotive industry with innovative solutions that meet its stringent demands for performance, quality, reliability and safety. Customers across the entire automotive supply chain are taking advantage GF’s technology offerings right now, from fabless semiconductor companies to Tier One suppliers to the automakers themselves. Here are a few recent developments I’d like to report.

On the Radar

Automotive radar technology is one of GF’s core competencies, and it’s becoming increasingly important as ADAS systems become more complex and widely used.

Radar is one of several sensor types used to detect objects near a vehicle, to enable features like adaptive cruise control. Lidar is another. It uses pulsed lasers to determine distance from an object by measuring the time it takes for the light to reflect back. However, lidar is currently expensive and is affected by weather conditions. Radar is less expensive, and higher-resolution radars promise to compete well with lidar in automotive applications, thereby enabling lower-priced vehicles to enjoy greater ADAS capabilities.

GF’s 22FDX technology offers great millimeter-wave (mmWave) performance and digital density for the next generation of 77-86 GHz medium-/long-range automotive radars. 22FDX-based radar sensors can provide higher resolutions and less latency than current radar sensors at a very low total system cost.

In the very near future, one of our customers will reveal how the company is using 22FDX as the basis of a radar imaging chipset that can detect obstacles at a range of 300 meters with a wide field of view at ultra-high resolution. Stay tuned.

Another example of how automotive radar is evolving comes from our work with a leading automotive electronics customer that is using GF’s mature CMOS process technology to develop a 77 GHz short-/medium-range radar module. The module integrates a microcontroller, digital signal processors, SRAM and flash memory, and support components on a circuit board replacing a much larger radar array.

Electric Cars with Better Range

Radar is just one automotive semiconductor application, of course. Powertrain control is another. At the recent Embedded World show, our customer Silicon Mobility demonstrated what the company calls a field programmable control unit (FPCU) for electric and hybrid vehicle powertrain control. Built with GF’s 55LPx CMOS technology, it offers real-time processing and control of sensors and actuators, coupled with a standard CPU, in a single semiconductor that conforms to the safety standard ISO 26262 ASIL-D.  Watch a live demo of Silicon Mobility’s electric automotive motor control, enabled by GF’s 55nm eFlash technology, here.

The result is a more powerful, flexible and safe architecture for the control and performance of electric and hybrid powertrains. By executing complex powertrain control algorithms quickly in hardware instead of in software, substantial energy savings and increased battery life can be achieved. The company says the FPCU can extend the range of electric and hybrid vehicles by some 32%.

Proven Quality in Dresden

Automotive customers demand much higher levels of quality and reliability than customers in other markets, which is understandable because we all know that cars and trucks must operate properly in all weather, road and traffic conditions over their entire service lives.

Consequently, semiconductor suppliers to the automotive industry must meet numerous quality standards and certifications that don’t apply to other types of customers. These are governed by a veritable alphabet soup of standards-setting groups and agencies, such as AEC, IATF, ISO, VDA and others.

We have already proven our automotive capability with our Singapore facilities and now I’m proud to report that GF’s Fab 1 in Dresden had its first full IATF16949/ISO9001 audit last month. Meeting this standard certifies that a facility’s quality management systems meet the requirements for automotive production. Conformance to it is essential.  Four auditors spent the better part of a week looking at all aspects and areas of the Dresden site. The result was successful and upon closing 4 actions within the next 60 days, the auditors will recommend Fab 1 for full certification.

These are just a few of the results of our push toward becoming a favored supplier to the automotive industry. It’s an exciting time to be in this business, as the electronics content of cars increases.  There are abundant semiconductor opportunities all along the value chain, and we’re going after them full speed.

Last year GF unveiled its automotive platform, AutoPro™, which provides a full range of technologies and manufacturing services to help carmakers harness the power of silicon for a new era of ‘connected intelligence’. For more information on the company’s auto solutions and service package please visit: globalfoundries.com/market-solutions/automotive.

About Author

Mark Granger

GLOBALFOUNDRIES’ Vice President of Automotive, Mark Granger, has been in charge of high performance SoC product design and product management for about 20 years, most recently at NVIDIA where he led the company’s efforts to provide leading-edge application processors for autonomous vehicles.

By: Khaled Douzane

An Introduction to the revolutionary and industry first FPCU (Field Programmable Control Unit)

As you probably know, the automotive industry is amidst a digital and electric revolution. Much similar to the evolution from flip phones to smartphones, vehicles are becoming electrified, autonomous, and connected, transforming mobility as we know it forever. What you may not know is semiconductors inside these cars are becoming more and more valuable, as they are the key to enabling electric and hybrid vehicles to conserve power, charge faster and reach new ranges. The world’s top auto manufacturers are judged on these key factors and are in a race to find the best technologies to reach the farthest vehicle range with the least power consumption with the fastest battery charging time.

Seeking of new technologies

The answer to this challenge is extremely complex as it involves several elements within an electrified powertrain system. From the battery technology and electric motor design to the motor positioning, there are limitless combinations of technologies to use in electric powertrains, and we are not diving into that conversation as it would be a very long article. The key to this discussion is the ability to control these new systems efficiently together in harmony for maximum performance with new a semiconductor designed specifically for electric and hybrid powertrain systems.

Amazingly, no adequate solution to date has been offered by traditional semiconductor manufacturers to control these new systems efficiently. Therefore, Tier 1 manufacturers and OEMs are essentially forced to use limiting technologies like multicores and microcontrollers that were designed for gas powered engines. Because of this, Silicon Mobility has engineered a new semiconductor called the Field Programmable Control Unit (FPCU) that enables existing electric and hybrid vehicle technologies to achieve their true potential.

A Semiconductor that surpasses the limits

This new disruptive FPCU semiconductor technology combines a flexible and parallel hardware architecture that offers real-time processing and control of sensors and actuators, coupled with a standard CPU. This is surrounded and complemented with an integrated highest standard safety architecture (ASIL-D) to form a single semiconductor. The result is a far more powerful, flexible and safe architecture for the control and performance of electric and hybrid powertrains.

The FPCU removes software bottlenecks and increases data processing over 40x faster than traditional semiconductors. The FPCU also enables up to 20x faster hard real-time control loop ensuring engine endurance and eliminating signal delays that can cause engine failure or damage. In addition, by executing complex algorithms in the FPCU hardware instead of software reduces power consumption significantly, reaching reductions of over 180 or 200 percent. This result of less power being consumed is an increased range of electric and hybrid vehicles. The FPCU has been measured to extend electric and hybrid vehicle range by over 32%!

Enabling the electric and hybrid revolution

By introducing the FPCU semiconductor, Silicon Mobility is helping automotive manufacturers and OEMs bring more efficient and custom designed electric and hybrid vehicles to market. Especially with the increased demand for extended vehicle range and increased data processing for autonomous driving, semiconductors like the FPCU are the key to achieving this without the need for rethinking or redesigning vehicle powertrain systems such as the battery or engine. Every top car manufacturer in the world is introducing at least one new electric or hybrid model in the next two years, and semiconductor solutions will be in extremely high demand. With the ability to increase vehicle range and data processing exponentially while reducing power consumption, semiconductor architecture is going to pave the way for electric and hybrid vehicle performance and range. Reason being, it is much less expensive to integrate new semiconductor architecture into existing powertrains than significantly alter powertrain system design and supply chains.

To learn more about Silicon Mobility’s FPCU called OLEA, please visit our website and learn about how this industry first semiconductor architecture can enable your electric and hybrid revolution.

Last year, GLOBALFOUNDRIES and Silicon Mobility successfully produced the industry’s first automotive FPCU solution. Most recently, Silicon Mobility successfully demonstrated its T222 chip at Embedded World 2018. This FPCU solution uses GF’s 55nm Low Power Extended (55LPx) automotive qualified technology platform to integrate multiple functions onto a single chip, boosting performance for hybrid and electric vehicles.

Watch a live demoof Silicon Mobility’s electric automotive motor control, enabled by GF’s 55nm eFlash technology.

About Author

Khaled Douzane

Khaled Douzane has 18 years of experience in the semiconductor industry with and automotive focus. As Silicon Mobility’s Vice President of Products, he is defining and driving all product lines for electric (EV) and hybrid (HEV) powertrain and autonomous vehicle applications. Khaled is a stakeholder in the patented technology design at the core of Silicon Mobilty’s innovative and revolutionary products. Prior to co-founding Silicon Mobility, Khaled contributed to the development of Scaleo, a semiconductor fabless company, where he held several roles, including SoC Desing Manager for eight years and Product Manager for an additional eight years. Khaled Douzane is a graduate of Nice Sophia-Antipolis POLYTECH engineering school with a major in Electronics.

By: Gary Dagastine

GF spoke 5G and the world listened at Mobile World Congress 2018

The Mobile World Congress in Barcelona, Spain is the wireless industry’s leading annual event, and this year’s edition in late February was buzzing with talk of 5G wireless technology. GLOBALFOUNDRIES seized the moment on the show’s very first morning with a special program on 5G’s evolving uses and technology requirements.

First, Gregg Bartlett and Dr. Bami Bastani, Sr. Vice Presidents of GF’s CMOS and RF business units, respectively, outlined 5G-related semiconductor challenges and opportunities for an audience of device developers, networking specialists and high-performance computing architects. 5G will impact all these areas because it enables smarter devices to feed through higher-bandwidth connections to ever-more-powerful data centers.

Then, a panel discussion moderated by Mike Cadigan, GF’s Sr. Vice President of Global Sales and Business Development, and head of GF’s ASIC business unit, took place. The panel was made up of invited experts from Nokia Mobile Networks, Mobile Experts LLC and TU-Dresden.

They gave insights into why 5G networks aren’t likely to roll out on a nationwide scale, why a one-millisecond network latency is “magical,” how working directly with a foundry can support more holistic solutions, and many other important considerations.

5G Computing Demands Optimized Silicon

Bartlett said 5G will drive profound changes in the computing requirements for devices and data centers, because the complexity and volume of network traffic are growing exponentially as the result of more users, more transactions per user and richer content per transaction.

“Data center applications will require very fast processors and near-100% uptime, while edge-connected devices will require chips with extremely low-power/low-leakage performance, and with embedded memory for storage and RF for wireless connectivity,” he said.

Both applications also will make use of artificial intelligence (AI) functionality but they will do so differently, he said. Data centers will use AI to learn, anticipate and direct the behavior of devices and networks, while edge-connected devices such as automotive cameras will use it locally for real-time processing and inference. 5G bandwidth is essential to support all these uses.

Bartlett said many companies will find it difficult to take advantage of 5G opportunities because of the significant investments required in design tools, EDA, intellectual property (IP) development and verification. “Many new, innovative companies can’t absorb these development costs, and they need technology solutions offering both competitive advantage and cost reductions going forward,” he said.

He explained how GF’s dual-technology roadmap offers this flexibility, with advanced FinFET CMOS technology for high-performance computing, and FD-SOI technology for wireless and battery-powered applications, both of which can be integrated with best-in-class RF functionality. Application-specific ICs, or ASICs, are another path forward to 5G, and GF offers the leading ASIC IP portfolio and more than 1,000 experienced engineers.

While many customers are clamoring for such wide-ranging, flexible foundry solutions, not all foundries are able to respond. “We have a growing portfolio of what I call ‘revolutionary’ customers, who are using new silicon as a wedge to break or change their industry’s traditional competitive framework,” he said. “They are demanding easier access to silicon and we have aligned ourselves accordingly to provide the optimized solutions they need.”

5G Connectivity Brings More Complexity

On the connectivity side, Bami Bastani said 5G will be rolled out in stages, leveraging the existing 4G/LTE backbone. First there will be enhancements to the existing system, then an initial rollout of sub-6GHz bands with massive MIMO architectures for high-rate transmission, and then a second rollout to expand network capacity and drive even higher data transmission rates by leveraging mmWave bands.

“This all means a more complex radio is required, one that works not only with new network protocols but also with legacy protocols and bands,” he said. “Thus, front-end modules (FEMs) must evolve in many ways as the transition from 4G to 5G takes place.”

Bastani said GF’s rich RF portfolio of silicon-on-insulator (SOI) and silicon germanium (SiGe) technology platforms creates differentiation for customers, as these optimized solutions can address specific customer performance, complexity and cost demands. He gave two examples.

For 5G basestations, control of the antenna arrays will require much more complex signal processing circuitry. “This process is called beamforming, and it can be done with analog, digital or hybrid circuitry depending on the size of the array. How the system is partitioned drives the choice of technology, and GF has a rich set of offerings to address all requirements,” he said.

The requirements are different for small mobile devices. “You’re now dealing with smaller arrays which require higher power per element to achieve the same radiated power. The good news is we can now do much of the beamforming digitally, thereby leveraging the scaling of advanced nodes like 22FDX to achieve low power and cost for these applications,” he said.

Industry Experts Outline the 5G Future

The discussion then shifted to a panel of experts including Joe Madden, principal analyst at Mobile Experts, Professor Frank Fitzek, head of the Deutsche Telekom Chair of Communication Networks at TU Dresden, and Michael Reiha, head of RF IC R&D at Nokia Mobile Networks.

Joe Madden started the panel dialogue, commenting that 5G networks will roll out differently than previous networking technologies. These were characterized by rapid surges of deployment because they enabled existing, widely used applications such as email to go wireless. By contrast, he said, 5G primarily benefits network operators and as-yet non-existent markets.

“From a network operator’s viewpoint the real advantage of 5G is cost. Today, it costs about $1.50 to deliver 1 GB of data over an LTE network, but with mmWave 5G it might be 5 cents or less,” he said, which implies there will be islands of deployment initially, such as in urban centers with dense network traffic or where it’s specifically needed for certain IoT applications.

Moving on to the topic of 5G standards, Cadigan asked Prof. Fitzek to describe the ways in which they are evolving, and how it relates to foundry technology. “Transporting more data isn’t really the issue, it’s all about latency. In that regard, why do we keep arguing that a 1-ms latency requirement is so magical? Well, it has to do with the physics of feedback loops,” said Prof. Fitzek. (Latency is the inherent delay in the network.)

He gave the example of a 50 Hz power plant feeding electricity into a smart power grid. A mere 10-ms of latency in the grid would result in such large phase shifts in the generator’s electrical output that it could be damaged, he said, whereas 1-ms of latency would be adequate.

“Many people think that if you put the wrong figure for latency into the standard, you can just fix it later. But it will be hard to fix, and to get the full value of 5G networks it must be there from the start.” This doesn’t pose a problem for semiconductor technologists, he said, because they are already very familiar with feedback loops.

The need for low latency is a major reason why Nokia designed its recently introduced 5G Reefshark chipsets itself instead of working with a fabless semiconductor company, according to Reiha. Cadigan asked him what that might mean for future foundry relationships.

Reiha said that to achieve such low latencies one needs to look at 5G requirements holistically, with a vision of the future that semiconductor solutions are flexible enough to support. “Nokia Bell Labs literally wrote the book on massive MIMO, and this enables us to understand the system-based challenges. We also understand the importance of seamless integration of semiconductor functions,” he said.

“What we expect from our foundries is an honest dialog and open access to IP to maintain our quality standards. We need quality IP because we can’t do everything, we’re not experts in all domains,” he said.

Cadigan went on and asked the panelists for their perspective on the approach GLOBALFOUNDRIES is taking in the 5G space. Madden said that GF’s ability to integrate various technologies is very important. “As we go to massive MIMO arrays, there is pressure to reduce the size of radio arrays as well as receivers. There can’t be large transmission lines, and multichip modules where everything is tightly integrated are essential,” he said. Cadigan noted the advanced packaging technology which came to GF from IBM.

Reiha said GF has the best-in-class RF capability, and that from Nokia’s perspective the continuation of ongoing device model improvements for RF is key. “This is especially needed for thermal device models and also for technologies such as SOI to enable more of a seamless mixed-signal simulation environment that would let us build many more sensors and put more control on our RF die, which would really let us focus on having an AI footprint at the antenna interface,” he said.

Prof. Fitzek talked about the importance of software and the openness of GF’s technology. “Because at this point you can’t really foresee what users will do, and machine learning will have its own purposes, your software APIs will only become more important in the future.”

About Author

Gary Dagastine

Gary Dagastine is a writer who has covered the semiconductor industry for EE Times, Electronics Weekly and many specialized media outlets. He is a contributing editor at Nanochip Fab Solutions magazine and also is the Director of Media Relations for the IEEE International Electron Devices Meeting (IEDM), the world’s most influential technology conference for semiconductors. He started in the industry at General Electric Co. where he provided communications support to GE’s power, analog and custom IC businesses. Gary is a graduate of Union College in Schenectady, New York,