By: Dr. Thomas Caulfield

Dr. Thomas Caulfield, CEO, GLOBALFOUNDRIES

2018 has been a volatile year by almost any measure, and the global electronics industry was at the center of the action. Soaring memory prices and tech stock valuations drove eye-popping growth in the first half, with Samsung solidifying its position as the world’s largest chipmaker and Apple briefly topping $1 trillion of market capitalization. Fast forward to the second half of the year and we muddled through falling stock prices, fears of a looming trade war, and a GPU inventory glut.

The “crypto hangover” described by Nvidia CEO Jensen Huang is an apt metaphor: After a night of celebration, we woke up in a stupor—rubbing our eyes and struggling to comprehend our surroundings.

To help clear our heads, we need to step back and look at the bigger picture. When the ground feels unstable, it is often a sign of seismic activity below the surface. Our industry is in the midst of a tectonic shift from the age of mobile computing to a new phase of growth that will be driven by a range of emerging applications such as IoT, artificial intelligence, and 5G connectivity. The number of connected devices will explode into the trillions, which will drive equally explosive growth in data traffic across worldwide networks.

Each level of the electronics supply chain is striving to adapt to the challenges and opportunities presented by this coming era of “connected intelligence.” Systems builders are adapting by developing infrastructure and devices designed to manage, analyze and act on this data—both in the cloud and at the edge. Chip designers are shifting their focus from general-purpose computing to domain-specific computing, where a uniquely defined architecture can dramatically increase performance and reduce power for a highly specialized application such as machine learning. And manufacturers are adapting to the impending demise of Moore’s Law. It is no secret that transistor scaling—the engine that has fueled the industry for nearly 50 years—is running out of gas.

So how can silicon foundries adapt?

At its core, Moore’s Law is an economic model. It is about delivering increased capabilities at decreased cost. Like all useful business maxims, it hinges on the ability to provide value. In the semiconductor industry, we have trained ourselves to believe that value creation only comes through transistor scaling. But in fact there are many ways to achieve the net effect of Moore’s Law, and they do not all require billions of dollars in annual R&D and capital expenditures.

In a data-centric world, power efficiency is a fundamental metric. Power consumed per bit must be minimized to further enable data-rate growth within a constrained power envelope. As we approach the limits defined by physics, shrinking transistors is no longer the best way to reduce power. The transition to domain-specific architectures in the data center and at the edge opens up new architectural possibilities, which can be supported at the manufacturing level through new materials, transistor enhancements and advances in packaging.

At GLOBALFOUNDRIES, we have been altering our course to adapt to the realities of this new era. I have laid out the rationale for our recent strategy change in multiple forums, so I will not rehash it here. I encourage you to watch this video interview with Dan Hutcheson of VLSI Research for additional context. While there has been a great deal of attention on our decision to refocus investment away from the leading edge, this “pivot” was just one piece of a larger transformation that is underway at the company.

As we continue this transformation in 2019 and beyond, we will make significant investments in R&D to enhance our existing technology platforms with an array of differentiated features. By adding a feature such as high-voltage operation to a more mature node, it transforms from a commodity-like process to a true value-added technology for clients. This is nothing new—our fabs in Singapore have been operating this way for years, and they have great margins to show for it. We are going to replicate this model across our portfolio, including our most advanced technologies. Our development teams have already shown that, through a combination of architectural, memory and packaging innovations on our 12nm platform, they can deliver almost double the improvement in power consumption compared to traditional node migration.

But these differentiated features will not be developed in isolation. They can only deliver real value if they are designed in partnership with innovative clients who are positioned to take advantage of high-growth markets. We are forming deep partnerships with a new breed of clients, engaging at multiple levels from silicon to systems. Synaptics is a great example. They have adopted our 22FDX technology as the sole platform for their next-generation voice and multimedia processing products for the IoT market. Our teams have worked hand-in-hand to take advantage of the unique features of 22FDX, such as ultra-low power operation and unmatched RF performance. You can hear more from Synaptics CEO Rick Bergmann in this video of his keynote at our GTC 2018 conference earlier this year.

For GF to be truly relevant, we need more than differentiated offerings. Clients have made it clear that they need a foundry partner with a sustainable business model, so they can be sure their technology investments can generate returns for years to come. We have placed a new emphasis on financial performance and we will continue to accelerate this focus in 2019 and beyond. Our decision to shift investment away from the leading edge has freed up a tremendous amount of resources, and we will look for additional ways to improve our cost structure. Expect to see more changes to our technology portfolio as we double down on the most differentiated offerings, and anticipate refinements to our fab footprint as we look to optimize our capacity profile.

GF will celebrate its 10th anniversary in March of 2019. Much has changed in our business and the broader industry over the past decade, but one thing remains the same: semiconductors are critical components of the global technology revolution. In 2018, the semiconductor sector is estimated by some analysts to surpass $500 billion. While impressive, this number significantly underestimates our industry’s contribution to the $2 trillion electronics ecosystem. As we grapple with a rapidly changing market and fundamental shifts in enabling technologies, we must collectively commit to capturing more of the value we create to keep driving innovation into the future.

About Author

Dr. Thomas Caulfield

Dr. Thomas Caulfield is the Chief Executive Officer of GlobalFoundries. Prior to being named CEO, Tom was Senior Vice President and General Manager of the company’s leading-edge 300 mm semiconductor wafer manufacturing facility (Fab 8), located in Saratoga County, NY. Caulfield, who joined the company in May 2014, led the operations, expansion and ramp of semiconductor manufacturing production at Fab 8.

Caulfield brings a track record of results through an extensive career spanning engineering, management and global operational leadership with leading technology companies. Most recently, Caulfield served as president and chief operations officer (COO) at Soraa, the world’s leading developer of GaN on GaNTM (gallium nitride on gallium nitride) solid-state lighting technology. Prior to Soraa, Caulfield served as president and COO of Ausra, a leading provider of large-scale concentrated solar power solutions for electricity generation and industrial steam production. Before that, Caulfield served as executive vice president of sales, marketing and customer service at Novellus Systems, Inc.

Prior to that, Caulfield spent 17 years at IBM in a variety of senior leadership roles, ultimately serving as vice president of 300mm semiconductor operations for IBM’s Microelectronics Division, leading its state-of-the-art wafer fabrication operations in East Fishkill, NY.

By: Dave Lammers

Faced with a slowing down of traditional markets and Moore’s Law scaling, the semiconductor industry is working hard to reinvent itself, to figure out the needs of new markets such as artificial intelligence, autonomous vehicles, the Internet of Things, and others.

Perhaps the most intriguing of these is artificial intelligence, with compute paradigms that can differ markedly from traditional processor-memory approaches. “For a long time, pattern recognition and cognitive tasks such as recognizing and interpreting images, understanding spoken language, and automatic translation were weak points for computers,” said Damien Querlioz, a French researcher who spoke on “Emerging Device Technologies for Neuromorphic Computing” at the recent International Electron Devices Meeting in San Francisco.

Since about 2012, progress has been accelerating in AI, both during the training and inference stages, but power consumption is still a huge challenge when traditional compute architectures are used. Querlioz, a researcher based at the French national laboratory CNRS, gave a telling example: the famous game of Go played in 2016 between Google’s AlphaGo and Lee Sedol, a world champion at the game. Sedol’s brain consumed about 20 Watts during their contest, while AlphaGo required an estimated >250,000 Watts to keep its CPUs and GPUs humming.

While power improvements have been made since then at Google and elsewhere, the effort to come up with new, less power-hungry devices for neuromorphic computing is intensifying.

Ted Letavic, senior fellow for strategic marketing at GlobalFoundries, said he thinks about AI in stages, a timeline moving from ways to improve conventional compute technologies to radically new devices and architectures that consume much less power. All along the timeline advanced packaging will play a key role.

“AI is upon us now, and we can use existing technology and add derivatives, using DTCO (design technology co-optimization) to optimize down to the bit cell design level,” Letavic said. GF technologists are developing ways to reduce power and boost performance for the 14/12 nm FinFET platform, including dual work function SRAMs, faster and lower power multiply accumulate (MAC) elements, higher bandwidth access to SRAM, and others. The FD-SOI-based FDX processes also consume much less power, especially when back-biasing techniques are deployed. With these technologies in the designer’s toolkit, Letavic said customers can “redesign the elements inherent to AI with a much lower power envelope than if they went right to 7 nm.”

In parallel to these DTCO improvements are the research and development efforts underway throughout the world for embedded memory and in-memory compute solutions based on phase-change memory (PCM), resistive RAM (ReRAM), and spin-torque-transfer magnetic RAM (STT-MRAM), and FeFET. A PCM-based chip, developed at the IBM Almaden Research Center headed up by Jeff Welser, has demonstrated great progress, Querlioz said at the IEDM tutorial session, and STT-MRAM- and ReRAM-based AI processors also show great promise.   “We now have a huge potential to re-invent electronics for cognitive-type tasks and pattern recognition,” Querlioz said.

Letavic said the long-range need to reduce power consumption, especially for inference processing, is driving a host of startups to develop new AI solutions, and GF is working closely with several of them, as well as with long-time partners AMD and IBM.

“We can only get so far with DTCO improvements to von Neumann computing. The next step beyond disaggregated logic and memory is to move to compute-in-memory and analog-based computing,” Letavic said. Moreover, the instruction set architectures (ISAs) that have served the industry well for 35 years will need to be supplanted with new software stacks and algorithms. “When we go to domain specific compute, someone has to reinvent the software. IBM has some really good insights about the software stack,” he said.

“Everyone has to take this turn toward AI together. Foundries will go hand-in-hand with lead customers, and we can’t separate algorithms from the technology,” said Letavic, referring to this close cooperation at STCO, or system technology co-optimization. “STCO is a natural extension of DTCO as we move into the fourth era of computing. As we move to domain-specific compute that is a shift we will all take together.”

Packaging to Help Reduce Costs

While silicon advances – including dual work function metals in the gate stack, FD-SOI, and STT-MRAM – will improve performance, Letavic said packaging will play an equally large role, as companies move to link heterogenous devices made with the optimum process for each function. “I think after 20 years of discussion, 2.5D and 3D are going to be mainstream. We will see as much differentiation, if not more, from the packaging as you will from the silicon flows.”

Kevin Krewell, principal analyst at Tirias Research, said work being done with Advanced Micro Devices will give GF an advantage as companies put two or more chiplets in a single package. Earlier, AMD and Intel combined an AMD Radeon graphics processor with an Intel CPU in a single package. Now, AMD is boosting its Epyc server CPU line by using AMD’s Infinity Fabric interconnect technology. The forthcoming “Rome” server processor will feature multiple CPU and cache memory chip cores, linking those 7nm parts to a 14nm chiplet fabbed by GF that provides the I/O links to DRAM and the PCI bus.

By dividing tasks and using the optimum process for each function, chiplets connected over high-speed links will change how processors for several markets are created, Krewell said, noting that Nvidia, Intel and others are supporting high-speed chip-to-chip links.

“Using a mix of process nodes in a chiplet design, I do expect to see more of that. The I/O especially doesn’t scale well to 7 nm, and those functions take up a lot of space, even in 7nm. Sometimes it makes sense to put the I/O functions in an older chip. Historically, PC chip sets were made in an N minus 1 process, as part of a fab utilization strategy. Putting those functions in the right process node that can handle the I/O, where it is not as expensive per transistor, makes a lot of sense,” Krewell said.

Letavic said systems companies are demanding heterogenous integration using various forms of advanced packaging ranging from interposers, vertical through-silicon vias (TSVs), special laminates, fan-outs, and others. The strategy will also provide a boon to photonic connections, as opto-electronics can provide higher bit rates than some electrical connections can support.

Bob O’Donnell, principal analyst at market research firm TECHnalysis, said the chiplet strategy still has a ways to go before industry-wide standards are nailed down. Until then, companies such as AMD and others will use their own internal technologies to link multiple chiplets into SoCs.

“At a certain point, complexity becomes overwhelming and then companies start to look to simplify again. The problem is coming up with a fertile ecosystem among multiple vendors, allow packaging companies to package different parts from multiple companies. Those standards haven’t been nailed down yet.”

O’Donnell said the effort to use the optimum technology for each function is largely motivated by the high-cost of designing and fabbing large SoCs in a 7nm process, for example.

“The basic concept with chiplets, ironically, is that we are taking apart things that had been integrated in the past. The industry was able to integrate systems into fewer components, all the way down to SoCs that had almost everything in a single chip. But now, there is a slowdown because it is just so much harder from a technical perspective. The design costs at 7nm are extremely high, and the challenges from a manufacturing perspective are just crazy.”

Letavic said advanced packaging will provide benefits “at the chip level and at the system level. We are seeing it in the data center already. It is here to stay, and it will just get bigger.”

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.