By Tim Nutt

This article was originally published on EDN and is republished here with permission. Read the original article on EDN. 

The rapid adoption of artificial intelligence (AI) across consumer and commercial markets is driving unprecedented investment in high-performance computing and networking. As AI models scale and proliferate across diverse applications, demand for compute power keeps rising. To meet this need, the power consumption of heterogeneous processing units (XPUs) is projected to climb from today’s 1–1.5 kW to more than 5 kW by 2030 [1]. This surge in power requirements is driving demand for denser, more efficient power conversion solutions from grid to core.  

The emerging power distribution architecture enabling AI scale 
Distribution of 415-480 VAC within datacenters causes a patchwork of electrical conversions. AC power needs to be converted to DC power to support battery backup, and back to AC for further distribution.  But as AI systems scale up, this energy loss is too costly to absorb. A key focus area for the industry is high voltage direct current (HVDC) distribution which reduces conduction losses, as well as the number of conversion stages across large clusters. 

The main proposed solutions are either ±400 V (Mt. Diablo) or 800 V (Kyber) DC power delivery.  The first phase of HVDC solutions will still rely on 415-480 VAC distribution with a sidecar power rack, thereby reducing some power conversion losses.  This step has fewer power conversion stages than existing systems and reduces conduction losses by delivering HVDC to the adjacent compute rack.  However, to further eliminate power conversion stages, data centers will distribute HVDC throughout the cluster.  Additional energy savings will be achieved by implementing the 800V DC-DC conversion within the system trays in compute racks, reducing busbar conduction losses. 

This deployment will require a significant step up in density and efficiency. The past few months have seen hyperscalers specifying their general needs [2] of higher rack-power capacity, power efficiency, density and scalability, as well as vendors responding with proposed converter topologies and considerations to meet those needs [3].   

This marks real progress, and it’s already clear that the key performance goals of the solutions are within reach. The benefits of these next-generation power delivery architectures include: 

1. High conversion ratio – Conversion from HVDC distribution to very low XPU core voltage with as few stages as possible requires a large step down ratio (>1000:1).  Solutions based on wide bandgap semiconductors such as gallium nitride (GaN) achieve higher conversion ratios due to higher breakdown voltages and reduced conduction and switching losses compared to silicon-based solutions. 

2. Significant density increase compared to current power supply unit (PSU) designs – The increase in XPU power consumption does not come with a corresponding increase in available volume for power electronics. Computer and network architectures impose a constraint on physical distance, creating a need for more compact power components. Thanks to their excellent switching characteristics, GaN power semiconductors can support higher frequency operation, allowing smaller energy storage components such as capacitors and inductors or transformers. 

3. Extremely high efficiency at scale – The extraordinary growth in datacenter power consumption means that power losses in every stage translate directly to energy costs.  Thus, the conversion ratio and high density must be achieved without sacrificing efficiency. GaN devices offer the best figures of merit – including including lower specific on-resistance, minimal switching charge, and better high-frequency FOM –  which result in the highest efficiency for a given ratio and density. 

How GaN is driving datacenter innovation 
The datacenter market demands not only advanced performance but also exceptional quality and reliability. Increasingly, industry consensus points to Power GaN as the key enabling technology for HVDC solutions in data centers.  

GlobalFoundries is developing GaN platforms to support this transition, including HV (650V) and MV (200V and below) devices. These platforms will offer industry leading figures of merit with the reliability and ruggedness that hyperscalers require to deploy AI at scale. 

Opportunities for Scaling HVDC Architectures
Looking ahead to broad solution deployment, there are several major opportunities that remain, each offering room to drive the next wave of innovation on topology selection and device optimization: 

• Establishing clear safety and isolation requirements: To date, safety and isolation have been discussed only in broad terms, but HVDC architectures will require isolation. Achieving safety and isolation compliance through spacing (creepage and clearance) can come at a significant cost to density, while achieving compliance mechanically via conformal coating or potting can degrade thermal performance – both of which complicate serviceability of systems in the field. Defining the right balance represents a major opportunity for innovation in materials, mechanical structures, and system architecture. 
• Defining EMI/EMC requirements for scaling next generation datacenters: With datacenters requiring strict electromagnetic interference (EMI) and electromagnetic compatibility (EMC) standards, the industry must determine how topologies can meet them. If bulky filter components are required to scale HVDC solutions, this may prevent density targets being met, potentially forcing alternate topology selection. It is crucial that these requirements scale to multi-GW datacenters allowing clusters to interoperate, otherwise compatibility and performance are at risk. 
• Converging on optimal step-down ratios and system-level power conversion strategy: Will the industry converge to a 16x or 64x step-down or, as the HVDC converter moves into the system tray, will system designers optimize the power conversion stages around different voltage levels?  If solutions are customized based on system-level optimization, this will likely lead to a need for regulated HVDC converters as well as unregulated fixed-ratio, with the two types having distinct transient requirements. These tradeoffs will affect overall system design in the future, from rack input to XPU. 

Enabling Scalable, Efficient, and Sustainable Datacenters 
As these solutions evolve and mature, GF will collaborate with our customers to optimize device development, integrate driver and sensor functionality with power devices, and heterogeneously integrate power devices with additional components.   

It is encouraging that along with the activity around converter feasibility, industry participants are also extremely active in pursuing open standards, such as the Open Compute Project’s Power Distribution sub-project, which will provide a roadmap for scalable, interoperable HVDC architectures.  

Adoption of HVDC architectures allows operators and OEMs to convert efficiency gains directly into XPU and network-cluster performance — delivering more usable Floating-point Operations Per Second (FLOPs) from the same energy footprint while reducing energy losses, lowering operational costs, improving rack-level density, and advancing sustainability goals through more efficient power delivery. Meeting these stringent demands at massive scale requires solutions that ensure interoperability and long-term ecosystem value remain top priority. 

注意事项。 

[1] Future AI processors said to consume up to 15,360 watts of power — massive power draw will demand exotic immersion and embedded cooling tech | Tom’s Hardware 

[2]  Asset Share – NVDAM  

[3] Swing Aboard the 800-V Bus: NVIDIA’s AI Power Architecture and the Chips to Drive It | Electronic Design 

Radhika Arora, VP/GM Pluggables Silicon Photonics
Kyra Ledbetter, RF Product Manager
Arvind Narayanan, Director, SiGe Product Line

As cloud infrastructure scales and AI workloads accelerate, data centers face unprecedented demand to deliver dramatically higher bandwidth with greater energy efficiency. While compute performance rapidly advances, the system bottleneck has shifted to the optical interconnects and transceivers that link these systems together.

Achieving longer reach, higher bandwidth density and lower energy per bit now demands a fundamental shift in optical module architectures – and the technologies that enable them. 

Leadership at 200G/λ: GF’s Scalable Silicon Photonics and High-Performance SiGe Solutions 
Data centers are rapidly approaching the limits of electrical interconnects, making silicon photonics the only scalable path forward. Enabling higher per‑lambda (λ) data rates, optical I/Os and packaging‑aware integration, GF’s silicon photonics solutions are redefining how bandwidth scales in next‑generation scale‑up and scale‑out architectures. 

GF’s silicon photonics technologies deliver the reach, bandwidth density and energy efficiency required to support the industry’s transition to 200G/λ and beyond. Combined with qualified 300mm manufacturing and wafer-level test capabilities, GF delivers a scalable, flexible, production-ready platform designed to evolve with future data rates and advanced packaging architectures – with capabilities including: 

• 200G/λ PAM4 support, fundamental to enable scalable 1.6T transceivers 

• Multiple modulator options for high-speed transmitter architectures, including Mach-Zehnder, MicroRing and RAMZI 

• High speed photodetectors enabling advanced receiver performance 

• Integration of silicon nitride (SiN) waveguides and spot‑size converters for higher optical launch power, improved coupling efficiency and long‑term reliability 

• Support for both v-grooves and standard edge coupled fibers  

• Through-silicon via (TSV)‑based 2.5D/3D integration to shorten electrical paths, reduce power and enable near‑package and co‑packaged optics at 1.6T  

As a compliment, Silicon Germanium (SiGe) remains a critical enabler of high‑performance optical transceivers – powering the analog and mixed‑signal electronics that drive and receive optical signals.  

After enabling industry‑leading 100G/λ deployments with our SiGe8XP technology, GF is positioned to lead the transition to 200G/λ with its added high-performance SiGe solutions – including 9HP+. GF’s SiGe 9HP+ platform sets a new benchmark in HBT performance, delivering ft/fmax of 340/410 GHz alongside one of the industry’s most complete BiCMOS offerings. Its combination of high‑speed HBTs, advanced CMOS integration, low‑loss metallization and high‑voltage LDMOS has made it the technology of choice for today’s highest‑performance optical transceivers. Beyond raw transistor speed, SiGe 9HP+ enables critical system‑level advantages: 

• Higher integration density for compact, thermally efficient designs 

• A robust portfolio of precision passives, including metal resistors, MIM capacitors and transmission lines 

• Industry‑leading PDK infrastructure and device models that accelerate design closure and reduce design iterations 

Together, these capabilities enable designers to meet the stringent power, bandwidth and aggressive form-factor requirements of the 200G/λ generation.  

A Unified Path from Optics to Electronics: Co-integration of Silicon Photonics and SiGe  
GF uniquely enables co‑integration of silicon photonics and SiGe, delivering a streamlined, end-to-end solution spanning optics, electrical ICs and advanced packaging. This comprehensive approach reduces system complexity, improves scalability and empowers customers to harness the strengths of both technologies – unlocking the speed, power efficiency and integration required to overcome today’s architectural stopgaps. 

Paving the Way to 400G/λ with Next-Generation Photonics and Advanced SiGe BiCMOS  
Enabling 400G/λ and beyond requires advancing beyond traditional modulator limits. As it is recognized that silicon alone will face increasing challenges beyond 200G/λ, GF continues to push the boundaries of silicon while also exploring novel materials. This includes a strategy centered around the hybrid and heterogenous integration of high Pockels effect materials – such as thin‑film lithium niobate (TFLN), barium titanate (BTO) and advanced electro‑optic polymers – directly onto our silicon photonics platform to enable ultra‑high bandwidth (>100 GHz) operation at lower drive voltage. 

GF has also introduced CBIC, the industry’s first SiGe Complementary BiCMOS platform, to support the leap to 400G/λ. By combining high‑speed SiGe HBTs with a flexible CMOS integration, CBIC enables new power‑efficient transceiver architectures optimized for extreme bandwidth demands – with key advantages including: 

• Industry‑leading NPN with ft/fmax > 400GHz, delivering enhanced analog performance 

• Support for innovative amplifier topologies that deliver high gain‑bandwidth with significantly reduced power consumption 

• A modular approach that allows customers to tailor cost, performance and integration for specific optical module classes 

Looking Ahead: Enabling the Future of Optical Systems 
As optical data rates advance toward multi‑terabit architectures, innovation across silicon photonics, SiGe and advanced packaging becomes increasingly critical. To empower this, GF’s roadmap focuses on continued HBT performance scaling and advanced 3D integration to enable tighter co-packaging of optical and electrical components.  

With a proven foundation and a clear roadmap, GF is committed to spearheading the evolution of optical connectivity technologies that will define the next decade of cloud and AI infrastructure. 

Interested in learning more? Connect with GF’s silicon photonics and SiGe experts at OFC and visit us at booth #817 to explore how we’re enabling the next generation of optical connectivity.