By: Nitin Kulkarni

Before the industry’s attention shifts to the next big international tech conference, MWC, I wanted to share some insights about CES. This year’s event was a record-breaker, with more than 3,800 exhibiting companies covering more than 2.6 million net square feet exhibit space. In addition the show welcomed more than 600 startups at the Eureka Park Marketplace – all showcasing the connected future of technology.

Here are a few top trends and takeaways from my experience walking the floor at CES 2017:

1. The connected home gets smarter, and more focused

Compared to CES in years past, this year appliances have gotten smarter because electronics companies are betting on consumers embracing smart personal assistant technology for the connected home such as voice activated appliances and smart LED bulbs that change color/ambience/intensity via a phone interface. Several companies were offering “smart home kits,” and a few products on display included smart speakers, smart lighting, smart appliances (white goods), home robots, even a smart mirror that will scan your face for wrinkles! Amazon’s Alexa was prevalent in several appliances.

Multi-node WiFi, also known as “whole home WiFi,” systems are becoming part of the “smart” home infrastructure as they can spread a WiFi network over a large area by simply adding a node where necessary without the need of an additional gateway or router. With the onset of Bluetooth 5.0, coupled with Bluetooth Mesh technology, the indoor wireless signal range can be quadrupled (from Bluetooth 4.x) to nearly 120 feet, essentially blanketing a home with coverage via multiple Bluetooth devices.

2. Virtual reality getting real

AR/VR/MR was everywhere! CES was the best place to get hands-on experience with some of the newest AR/VR devices. We saw everything from boots that enable you to feel the digital worlds you’re walking through to a candle that lets you smell.

At the forefront of mobile AR/VR was Qualcomm®’s Snapdragon™ 820/835. The 835 was being promoted for AR smartglasses for mobile entertainment and computing. VR is also one of the key areas that requires extreme performance PC designs based on faster and more advanced architectures.

3. Smarter, smaller drones

Drone technology can now support more advanced tech features such as real-time obstacle detection and avoidance during flight.

Many drones supported 4K camera, 10-30min flying time, 2.4GHz WiFi, high-precision GPS modules with improved location accuracy (some support Follow-Me mode), some with 360 degree view. Battery life is being continuously improved by advances in battery management design as well as software algorithmic implementation in drone architecture. Some drones displayed included more advanced features such as real-time 3D terrain/surface mapping that can be used in in industries such as agriculture, land/resource management and building/architectural visualization.

Today toy drones for recreation/hobby are available for less than $100 as well as high-end and advanced functionality drones (with longer flight times and operating ranges) that exceed $2500.

4. Electronics merging with automotive

This year there was a real synthesis between the automotive and electronics industries, with hundreds of automotive companies showcasing their new automotive technologies ranging from self-driving systems and electric cars to new user interfaces.

Digital know-how is now required to implement autonomous driving. New platform highlights included integrating gigabit-class LTE connectivity to the car with high-bandwidth in-car connectivity over WiFi, ethernet, BT and BLE. Other show “drivers” included top-tier auto-makers announcing integration of a new UI concept which is a virtual free-floating display controlled via finger gestures and new partnerships for an AI-powered car by 2018.

Audio and speech recognition technologies will play a huge role going forward – as showcased by the integration of Amazon’s Alexa and Microsoft’s Cortana digital assistant by a variety of automakers. Moreover, the car is an extension of a user’s digital and social connectivity, and vehicle infotainment (IVI)bsystems require additional storage space for rich multimedia data and advanced software and applications. GF’s FDX technology platform empowers IVI systems for automotive.

5. Wearables grow up

The wearable market has spread well beyond the confines of wrist-based technology. We saw smart hair brushes that coach you to be a better brusher to a new line of clothing designed to improve sleep quality to headphones that claim to prime your brain for faster adaptation to exercise – a lot of cool digital-health tools on the horizon.

Wearables along with other electronic devices are a big part of IoT, and they will play the role of data producers. An example would be wearable health devices. Since the physical data collected by the things at the edge of the network is usually private, processing the data at the edge could protect user privacy better than uploading raw data to the cloud.

Consumer electronics have become increasingly important in driving the entire global tech industry, and CES is the place that points to a more connected future. With increasing numbers, various devices are going online and networking with each other as well as users interacting with their devices in new ways.

Networks which carry the data traffic and Data Centers that harness and transform the raw data to faster decision-making insights and outcomes are driving new requirements for semiconductors that are power efficient, optimized, and cost-effective for IoT nodes. We are starting to see the shift to leading-edge 28nm, 22nm, and 14nm (and beyond) process technology, and a growth in edge-node computing. GF’s CMOS, RF and ASIC technologies address this leading edge shift. Specifically, our FD-SOI (FDX) and FinFET platforms target both the high and mid-end markets.

Critical to this is the ability to sense, process, control, and communicate in a highly energy and cost efficient manner. Some essential requirements for IoT devices include low power, cost-effective performance, RF connectivity, superior analog/power integration and smaller packaging. All of these IoT trends play well in the direction of GF’s technology offerings –low-cost, efficient, scalable and reliable solutions. Our unique FDX portfolio supports multiple wired and wireless products across a range of applications includes the industry’s lowest power RF solutions where GF is the established market leader in RF SOI, to serve the demanding needs of IoT.

Semiconductors have a tremendous role to play in enabling these cool, new devices we see every year at CES — a technology opportunity of a lifetime.

GLOBALFOUNDRIES, the GF logo and combinations thereof are trademarks of GF Inc. in the United States and/or other jurisdictions. Other product or service names are for identification purposes only and may be trademarks or service marks of their respective owners. Use of those names, logos, and brands does not imply endorsement.

All photographic images provided by Nitin Kulkarni, GF.

By Dave Lammers

Now that magneto-resistive random access memory (MRAM) has reached the point — after more than two decades of development — where it can be more widely used, the question becomes: How will designers use it? How will MRAM make a difference in the connected systems in mobile, automotive, and IoT? MRAM pioneer Everspin Technologies (Chandler, Ariz.) has been shipping discrete MRAMs made by GF, largely to the cache buffering market, for the past two years, said analyst Tom Coughlin. With speeds rivaling DRAMs, and basically unlimited data retention, Coughlin said MRAM “is the best candidate for replacing existing non-volatile memories in computer architectures.”

Mobile devices and other systems often have large amounts of SRAM, Coughlin said, and must use time and energy to preserve the memory state when the power is turned off, or a system gets hung up. Because MRAM can be turned off and on with virtually no additional power consumption, system designers can do much more power cycling, turning power off to conserve battery life. There is no energy penalty when a normally-off system comes back to life. “For mobile devices, MRAM enables a lot more power-saving modes, which can help battery-powered systems,” Coughlin said. MRAM’s power-saving capabilities are somewhat surprising, because the early knock on MRAM was that it consumed a lot of power. Over the past 25 years the technology has gone from a thermally-assisted, sandwich-layer MRAM to a perpendicular magnetic tunnel junction, spin-transfer (pMTJ ST-MRAM) architecture. Back to the question: Where does MRAM fit? First, think about how fast the electronics industry is changing and where the opportunities are. New product categories such as augmented reality systems, assisted driving vehicles, drones, and a panoply of IoT technologies, are right in front of us. Dave Eggleston, the vice president of embedded memory at GLOBALFOUNDRIES, points out that most of these new systems depend on fast visual image processing. A car must process image data in real time to avoid a crash, requiring visual image processors and fast memories. “A drone is a great example of where you need lighter weight, and where more energy-efficient circuitry results in longer fly times. How does a drone navigate? By pulling in 3D maps. It has its own vision system, with stored information on topography, to hash real-time information,” Eggleston said. With MRAM, it is possible to trot out some impressive characteristics: 1000x more endurance and 1000x faster write speeds than eFlash; more dense and versatile than SRAM, and an ability to integrate into a CMOS logic process without disturbing the logic transistors. Also, embedded MRAM (eMRAM) is a low-mask-count technology, requiring only four additional mask layers compared with a dozen or more for eFlash at advanced nodes. Early on, Eggleston didn’t envision MRAM being immediately suitable to embedded applications. “I’m not sure I would have told you that ten years ago. But because the magnetic junctions are built in the back end of the line, and are easier to integrate in a logic process, the embedded applications make sense,” he said.

MRAM as Working Memory

To think of eMRAM as simply replacing something else probably is not the best way to think of it, especially in the advanced SoCs needed for emerging markets. It opens new possibilities in the working memories for mobile, IoT, automotive, and other connected applications, Eggleston said. For a complex chip with, say, four graphics processing units and a visual processing unit, an MRAM module could store the code and another block of eMRAM could store data. “By storing data in a non-volatile media, you don’t get rid of SRAM, because eMRAM does not run as fast, but you can shrink down the amount of SRAM and utilize eMRAM as an SRAM-like memory. That makes the design cost effective because eMRAM is denser than SRAM. You get more data for a smaller chip size,” Eggleston said. Software and SoC designers will learn new capabilities, taking advantage of the “persistence” (data retention) characteristics of eMRAM. The cost and performance benefits of eMRAM are what Eggleston calls the “table stakes” needed to make eMRAM a credible alternative to eFlash. But it will be the new capabilities brought by eMRAM that will entice system designers to ask ‘Now, how else can I use it in my chip architecture?’ Coughlin, who earlier worked in technology management at several disk drive companies, said MRAM “definitely has a niche replacing some DRAM and SRAM. It may replace NOR. What we are seeing is almost a Cambrian explosion in the memory field, where NAND flash will continue for mass storage while we see another tier of storage where MRAM or the Intel-Micron phase change memory is used in some applications.” As new applications call for higher performance, and as IoT systems generate much more data, systems designers will use multiple layers of memory. SRAM and DRAM will be complemented by new layers of phase change or resistive memories, and NAND, Coughlin said. “It will be a very interesting time, and we will see how it all shakes out. I do believe MRAM has a solid basis for being part of that menagerie,” he said.

22FDX® eMRAM

Eggleston said GF will continue to extend embedded flash, but GF’s plan is to marry eMRAM with another technology that has mask-count advantages: the 22FDX platform based on fully depleted SOI. The 22FDX-based products will begin to come to market in 2017, and Eggleston said eMRAM becomes available the following year. That timeline contrasts with a normal four or five years to bring NVM to a new logic technology. “For customers that need embedded memory, to bring eMRAM to 22FDX so soon after the (22FDX) logic launch is a huge win. With eMRAM, customers don’t need to recharacterize their designs, because the eMRAM is an extension of the platform, not a platform in and of itself,” he said. Since eMRAM does not shift the underlying transistors, designers can efficiently build a 22FDX-based SoC with the integrated eMRAM that runs on a logic voltage. “eMRAM is straightforward, it integrates incredibly well, and runs on a logic voltage,” he said.

Manufacturing Experience

Other companies have publicly referred to their own MRAM development programs. Coughlin noted that Everspin, which earlier took CMOS logic wafers and added its MRAM to the back end of the line, now works with GF as its full manufacturing partner. The 256-Mbit and, soon, 1 Gigabit-density discrete MRAMs sold by Everspin are made by GF. Coughlin estimates that about 60 million discrete MRAMs have been sold by Everspin thus far.

Source: Everspin, MRAM Leadership Over Three Generations

The years of manufacturing experience GF has gained by working with Everspin have provided key learning in deposition, etch, metrology, and other manufacturing processes that are unique to the multi-layer magnetic stacks within MRAMs. Coughlin said the manufacturing and technology partnership with Everspin has provided GF with a lead in the eMRAM arena. “I think it is a very important, pioneering effort. It has given the partners a lead in actual products, but they must be diligent to keep their lead,” Coughlin said. Eggleston said the spin-transfer MRAM work between GF and Everspin has provided “a lot of learning cycles” over the past two years of running wafers. “By the time we are in production with 22FDX eMRAM we will have been fabricating MRAM for four years. That definitely accelerates the time to market for our embedded solution,” he said.

GLOBALFOUNDRIES’ VP of the ASIC product line shares how the team’s rigorous approach to design implementation and methodology were critical factors in achieving first-time silicon success for a major networking customer. Designing complex ASICs and delivering them on time is no easy task. It requires a powerful combination of design expertise, proven methodologies, and robust process technology. One year ago, with the launch of GF’ first ASIC platform, FX-14®, we gained competitive ground with a new pipeline of ASIC offerings on our 14nm FinFET process technology (14LPP). Since then, we have combined a rich legacy of ASIC expertise from our acquisition of IBM Microelectronics with manufacturing scale and improved access to IP and design tools to enable a new generation of customers to easily adapt their chip designs to the FX-14 offering.

GF has decades of high-speed interconnect, memory, processor, and packaging innovation

Today, I am pleased to share an exciting milestone in our journey: We have achieved first-time-right silicon success for a lead product using our FX-14™ ASIC platform, with a major networking customer (to remain anonymous) bringing up a board in one week and declaring a fully functional ASIC chip. Such an aggressive schedule would be impressive for any product, but this is no ordinary chip—the highly complex design incorporated a high-performance ARM® 64-Bit core, a DDR memory subsystem including DDR memory controllers and PHYs, multiple high-speed backplane SerDes covering a broad range of interface standards, dense 1- and 2-port SRAMs, high-frequency I/Os, and PLLs. How did we accomplish this? A key factor in our approach is the use of an integrated test chip based methodology to rigorously vet our design implementation and methodology well in advance of customer product tapeout. Our ASIC design-for-test features include full scan, IEEE 1149.1 and 1149.6 JTAG boundary scans, and complex IP that meets the IEEE 1687 standard. Additionally, we use a three-phase netlist signoff process with stringent entrance and exit milestone requirements. This type of ASIC platform rigor before product tapeout is essential to enabling first-time customer success. Another key contributor was the maturity of the 14LPP manufacturing technology at our Fab 8 facility in upstate New York, which is in high-volume production on multiple products. By leveraging the FX-14 design platform, the team was able to turn around defect-free parts quickly in order to guarantee first-time-right silicon, while also achieving a power reduction of more than 50 percent over the customer’s previous design. Achieving first-time-right silicon success and fast board bringup for such a complex chip demonstrates the power of GF’ ASIC FX-14 design system. This, along with our proven expertise and design methodology, helps ensure that our customers can design with confidence and achieve a fast path to volume production. Today, we have many customer designs underway in FX-14 across a number of segments, including wired networking, wireless base station, compute, storage, and aerospace and defense applications. We are committed to partnering with these and other customers to help them bring their most complex designs to market.

By Sanjay Charagulla

Cloud computing and high-performance computing (HPC) are changing the data center industry in a big way. The biggest drivers in this space are consumerization and big data, putting our trajectory on steroids. Global cloud IP traffic will more than quadruple over the next 5 years, growing at a CAGR of 33 percent from 2014 to 2019, and accounting for more than 80 percent of total data center traffic. Also, more than 86 percent of workloads will be processed by cloud data centers. As the rapid pace of change continues, server computing and data storage requirements will continue to grow at a significant rate across the data centers, resulting in data center OEMs deploying more and more servers and storage.

Source: Cisco VNI Global Cloud Index, 2016

 

It was only a few years ago when companies were debating if they were ready for the cloud. Today, it’s no longer a question of if – it’s about how much they can get out of the cloud services. Server processor shipments are estimated to grow by an average rate of nearly 25 percent CAGR for the next four years, reaching a total of about 25 million processors. For example, out of 11+ million servers shipped last year, x86 chipsets were used in 9.8 million of them. In the second quarter of 2016, Intel accounted for 99.7 percent of x86 server-chip shipments. The cloud is also forcing changes to long established players in the hardware and software worlds. Recently, IBM unveiled new details of its Power9 chip —the next addition to the line of microprocessors the company plans to use in its own servers—and AMD announced its new Zen technology for server chips. Here is IBM’s official Power processor roadmap from last year, and see how AMD’s Zen microarchitecture is different from its other server cores. As data server companies seek to increase power and performance while reducing costs, chipmakers are up to the challenge to find ways to increase speed and functionality to devices while keeping costs low. For example, because of its competitive power and performance, with a ~10 percent lower die size, GLOBALFOUNDRIES’ advanced 14nm FinFET technology (14LPP), supports a wide range of products from mobile devices to servers, such as AMD and IBM’s server chip products. Enabled chip x86 processor performance by 3GHz+, the GF’s 14nm FinFET technology taps the benefits of three-dimensional, fully-depleted FinFET transistors, and offers impressive gains over 28nm bulk CMOS with up to 50 percent increase in performance and a 65 percent reduction in total power.

Source: GF Technology Conference 2016

The IBM and AMD announcements along with GF competitive advanced node technology, represent new competition to Intel’s dominance in the server market. In a recent strategy shift, IBM’s Power9 architecture will be offered to other hardware companies. Subsequently, IBM Power9 processors are not only targeting to HPC and enterprise server markets, but also enabling solutions for big data analytics, artificial intelligence, cognitive and hyper-cloud computing platforms. At a Silicon Valley technical conference this summer, AMD rolled out a demonstration of the performance with a head-to-head comparison of its Zen Core, claiming a 5x improvement in cache bandwidth with the redesigned memory subsystem. Overall, it is a core that contributes a 75 percent higher capacity to schedule instructions and a 50 percent greater ability to execute and issue them. With the advent of cloud computing, large service providers such as Google, Facebook, and Amazon are opting for systems based processors and open-source or in-house applications. Earlier this year, Google announced that they are working with Rackspace to co-develop an open server architecture design specification based on IBM’s new Power9 CPUs. The partnership with Nvidia should also help IBM’s Power9 become popular in servers as well as in supercomputers. Along with these two server giants, many other ARM processor-based chip vendors and other startups are building ARM server chips to target cloud data center markets. ARM estimates that 13 companies already are using its technology in chips for servers and other data-center hardware, which are expected to compete predominantly in single-socket and dual-socket servers with Intel server chip products. Server companies and other ARM based chip vendors are aiming at Intel’s chip dominance, targeting the~$12B server market for scale-out data centers. Overall in the next few years, these processor technologies and new solutions could begin driving a 15–25 percent growth in the server chip market.

By Fernando Guarin

A Bit (or Byte) of History At the time that I started mentoring students with Snap Circuits at IBM in 2006, we were looking for creative activities that could convey to students what an electrical engineer does on a day-to-day basis. We started using the kits with local schools during Engineer Week visits, then expanded to the week-long camps we hosted for girls during the summer. Since 2008, I expanded my involvement in mentoring to the IEEE’s Electron Devices Society (EDS) and, with the organization’s support, have been working with a number of engineers to inspire young minds through a worldwide mentoring program called EDS-ETC (Engineers Demonstrating Science: an Engineer Teacher Connection). Formally introduced in 2010, the program was designed with the help of volunteers from the Rochester, Boise and the Mid-Hudson Valley Chapters in New York. These dedicated volunteers ran initial evaluations working with their local science teachers ranging from the fourth through twelfth grade levels. In the first phase of the project, Snap Circuits kits were made available to chapters in the United States. Shortly thereafter, the program was expanded to EDS chapters throughout the globe with participation from all IEEE regions, where local EDS chapter student members have been actively engaged. Now, the only requirement for chapters to receive kits free of charge is that they submit a plan indicating how they intend to use them. In 2015, more than 9,000 young students participated in over 130 events around the world

Engineering a Difference

The main goal of the program is to enable chapter members to visit local schools and host events designed to engage young students in the field of electrical engineering. By utilizing easy-to-use Snap Circuit Kits, students learn about electronic circuits using a “hands-on” approach to experience the exciting and creative field of electronics. We hope to encourage them to consider electrical and electronic engineering as a career. This versatile tool, along with EDS volunteers’ enthusiasm and expertise, has been used to demonstrate the many applications and motivate young students into the exciting electron devices field. In order to make a difference in the world, we need to start by working within our own communities and local schools. We need to partner with local government and industry to inspire the next generation of engineers and scientists that will work to solve the most pressing challenges we face in the world – clean water, wind/wave/hydropower, photovoltaics/solar cells, managing waste, geothermal, energy crops, energy harvesting, health care and many more. There will be plenty of work for the next generation of engineers. The technologies that advanced manufacturers develop and deliver to their customers will shape the future. We all need to contribute in order to keep the pipeline of engineers going by sharing our knowledge with the young minds that will ensure a bright future for our planet. Get involved today! Check with your employer to learn about available education outreach programs. Organize a maker faire or team up with local teachers and co-workers to get a mentoring program started. Snap Circuits kits are a great way to get students of all ages engaged. Other options include Raspberry Pi™, Arduino™ and more! Click here for additional information about the IEEE EDS-ETC program and to view a related video.

By Dave Lammers

Of all of the numbers claimed for the GLOBALFOUNDRIES fully depleted SOI technology, the one that stands out in my mind is 39. That is the number of mask layers required to create a 22nm fully depleted SOI chip, one with eight metal layers. And it compares, said Jamie Schaeffer, the FDX™ program director, with 60 masks for a comparable chip with FinFET transistors. Of course, comparisons between FinFET and FD-SOI technologies are inexact. Each have their merits. With FD-SOI, the starting SOI wafer costs several times more than a bulk wafer. There are drive current differences. But consider how many more delicate fin-creating etch steps, how many more multi-passes through expensive scanners, are represented by those extra 21 mask layers. Then it starts to become clear that FD-SOI may provide cost advantages that were not really there when the competition was between bulk planar and SOI planar technologies.

Continuity Concerns

22FDX® designs are prototyping now, with risk production in Q1 2017. The recently announced 12FDX™ technology moves to commercial production in 2019. Dan Hutcheson, CEO of VLSI Research Inc., surveyed 75 decision-makers at six chip companies, six EDA and IP vendors, and two universities, and found that one of their concerns was continuity. “One of the issues expressed in the survey was ‘Is there a future?’ They wanted to make sure there was a next node” to FD-SOI technology. Schaeffer also tagged the importance of the succession factor. “The entire FDX roadmap, integrating 22 and 12FDX, provides a complementary path to FinFETs,” he said. However, Schaeffer took slight umbrage when I asked a question that implied that the real volumes will remain in the FinFET arena, with processors and graphics chips, while FDX would be well-suited to the smaller potatoes, to the design teams that didn’t quite have the resources to tackle a FinFET project. “We are not doing this as a niche technology,” he replied. “We are targeting high-volume opportunities—transceivers, WiFi, vision processing, and automotive. We intend to fill a large volume of our Fab 1 in Dresden, and have plans in place from a capacity perspective,” Schaeffer said.

GLOBALFOUNDRIES 22FDX is Manufactured in Europe’s Largest 300mm Factory

That word, transceivers, is key to the FDX program. The 22FDX transistors exhibit an F_max in the 325 GHz range, capable of meeting the nascent 5G cellular specification. Schaeffer said that the 22FDX and 12FDX technologies provide “a unique opportunity to integrate mmWave transceivers with ADCs, DACs and digital baseband. FinFETs provide the digital scaling but not the RF performance that is needed at mmWave frequencies. In the IoT market, FDX technology could support microcontroller-based SoCs with integrated low-power wireless. It also could come into play for products based on the new gigabit-class WiFi standards. And depending how quickly the 5G cellular standard is firmed up and how it fits in with the assisted-driving cars of the future, FDX may find large volumes in the automotive space.

Analog Friendly

Hutcheson said he was skeptical of SOI until he undertook the VLSI Research survey, and talked to device physicists about the relative merits of FinFETs and SOI transistors. “When we surveyed design engineers, they said that for analog, SOI is much better than FinFETs.” Dick James, senior fellow at ChipWorks (Ottawa), said that analog designers depend on an ability to adjust the width of their transistors. With FinFET-based circuits, designers deal with “a quantized transistor width,” adjusting transistor widths by using multiple fins. “With planar transistors, analog designers can tune their circuits by putting wider transistors wherever they want,” James said. The debate over power consumption also tilts in favor of SOI, James said. With the buried oxide layer (BOX), “every transistor, theoretically, can be surrounded by an insulation layer, and that helps control leakage and parasitics.” Back-biasing also plays a role in controlling power by raising the threshold voltage and reducing leakage where appropriate, he said. The debate over the relative merits of bulk FinFETs versus SOI technology has been going on for decades now, picking up intensity in the summer of 1998 when IBM formally announced that it would turn to SOI for its server processors. Intel vehemently supported its continued path on bulk silicon, ultimately leading to FinFETs, which have occupied center stage for much of the last decade. Now the FD-SOI or FinFET debate – where each fits in today’s technology spectrum — is reaching a new level of intensity, one that will play out in the marketplace.

But why 22? Why not call it FDX20? And why 12, instead of using the 10nm delineation favored by others? This goes back to the cost-of-production issue. With 22nm design rules, Schaeffer said, single-pass patterning is sufficient. No double patterning is necessary. With 12nm, double-patterning gets the job done on critical layers, obviating the need for triple or quad patterning. There you go. With 39 mask layers, superior carrier frequencies at low power, FDX could provide an alternative to FinFETs, especially in markets where the combination of transistor density and good RF performance is valued. Let the competition begin.

Foundry Files Guest Blog

This article originally appeared in The Chip Insider, August 7, 2015, and is printed here with permission from VLSI Research, Inc. GLOBALFOUNDRIES’ 22FDX is the first radically new process since Intel introduced the first working finFET process. You may have noticed an omission on my part for some time. That is I’ve never written much about FD SOI over the years. The reasons are pretty simple. First, I didn’t have anything positive to say that I really believed. The problem with FD SOI has been that it’s only salable advantage was that it was cheap. And even that was in question, because the big dogs didn’t bite — and they’re all about lowering cost. Even if it was cheaper, no fabless company is going to risk its future on lower wafer costs. The upfront NRE costs of a new design, time-to-market constraints, as well as the consequences of failure should it not yield, overwhelm the promise of cheaper wafers. The giga-fabbed chip makers know this, so they won’t move until their customer moves. That’s all changed with 22FDX. The big advantage of 22FDX is the ability to have real-time trade-offs between power and performance via software-controlled body-biasing of the transistor. Yes, there are real time power consumption trade-offs that can be made at the device level — mostly by turning on-and-off major functional blocks. But to the best of my knowledge it’s never been at the transistor level on a market-worthy process. If this works like they say it does, 22FDX will be a major revolution that will be disruptive throughout the electronics industry. Here’s why: Imagine a future where you could set how many hours your battery will last. Right now, the best thing an OEM can do is shut certain functions off as power dwindles, such as how the Apple WATCH does. But with 22FDX, you could potentially set your watch to something like, ‘run until 9 PM, when I expect to take it off.’ And then change it to later or reset it the next day if you wanted. Then the watch would match its power-performance trade-off to a prediction based on your typical use and then modify its performance based on how you’re using it that day. It would work the same way on phones, laptops, and just about any mobile electronics you can think of. Now how cool is that! This guest article was written by Dan Hutcheson, CEO and Chairman of VLSI Research Inc. Hutcheson is a recognized authority on the semiconductor industry, winning SEMI’s Sales and Marketing Excellence Award in 2012 for “empowering executives with tremendous strategic and tactical marketing value” through his e-letter, The Chip Insider®; his book Maxims of Hi-Tech, and his many interviews of executives. Dan’s public work on the industry includes two innovative articles for Scientific American challenging predictions of the demise of Moore’s Law by demonstrating how scientists’ innate abilities to innovate have outpaced the doomsayers and an invited article on the history and economics of Moore’s Law for the SIA.