By: Dave Eggleston

There’s been a lot of news recently about embedded MRAM (eMRAM), and for good reasons.  The technology is rapidly accelerating from research and development to commercialization at multiple foundries, and is now being adopted by chip designers. Most notably, GLOBALFOUNDRIES just announced the availability of its 22FDX® 22nm FD-SOI eMRAM for system-on-chip (SoC) designers, with released PDKs, off-the-shelf macros, and MPWs for customer prototyping. With risk production expected from GF and other foundries by the end of 2018, MRAM is shaping up to be a big technology and market disruptor right now, promising to replace embedded Flash, and augment SRAM in MCUs and SoCs for automotive, IoT, consumer and industrial systems. Over the horizon, FinFET processes with eMRAM will also appear, bringing new capabilities to future storage, networking and data center systems.

Supercharged Performance

MRAM technology has been under development for decades – in parallel with several other non-volatile memories including RRAM, Phase Change, Carbon Nanotubes, Ferroelectric – and recently, eMRAM has clearly taken the lead position among all emerging embedded memory technologies. Why? eMRAM offers SoC designers very significant performance advantages:

• Very fast write speeds (<200ns)
• Extremely high endurance (~10E8 cycles)
• Operation from logic Vcc (no high voltage pumps needed)
• Low energy writes (10x lower than eFlash)
• Zero bitcell static leakage (0 pA vs. >50pA for a SRAM bitcell)

Coupled with the performance advantages, eMRAM enjoys a significantly higher level of technology maturity versus other emerging NVM options, featuring:

• Well understood magnetism physics
• Simple, controllable switching mechanism (no forming, or stepped writes needed)
• Low incidence of single bit failures
• Demonstration of multi-Mb arrays at sub-28nm
• Achieving high yield, with excellent reliability
• Full integration into advanced foundry production processes

eMRAM simultaneously delivers bit density, speed, endurance, coupled with low power consumption and non-volatility. The combined advantages of superior performance and technology maturity for eMRAM are key factors for foundry customers deciding to use eMRAM for their sub 28nm products.

Hit the Road Running

eMRAM simultaneously delivers bit density, speed, endurance, coupled with low power consumption and non-volatility. The combined advantages of superior performance and technology maturity for eMRAM are key factors for foundry customers deciding to use eMRAM for their sub 28nm products.

Historically, eMRAM has not been perceived as ready for commercialization because of several manufacturing and reliability barriers: material complexity, poor data retention at hot temperatures, susceptibility to external magnetic fields, and finally, difficult and expensive manufacturing.

Tough challenges to overcome, but to move the needle from an unreliable to reliable technology the industry has directly tackled the issues of materials and manufacturing complexity. As a part of this effort, major fab equipment makers, along with foundries, pioneered eMRAM specific PVD and Etch equipment that achieves 20 wafers per hour (wph) throughput, which enables a competitive manufacturing cost.

Moreover, GF has specifically improved eMRAM reliability, by modifying the magnetic materials to deliver outstanding data retention and magnetic immunity, including:

• Less than 10ppm bit error rate through 260°C solder reflow
• 15 year data retention at 125°C
• More than 1000 Oe magnetic immunity

In other words, many of the past barriers for eMRAM commercialization have now been overcome – solved by the collective efforts of the foundries and major fab equipment makers in making eMRAM reliable and manufacturable.

Crank up the “Killer Combo”

In light of these new advancements in reliability and manufacturability, high-volume market opportunities have now opened up for eMRAM. The market opportunity further expands with the widespread commercialization of fully-depleted silicon-on-insulator (FD-SOI) as a substrate.

eMRAM on FD-SOI brings together best-in-class capabilities, creating an irresistible “Killer Combo” vs. other bulk silicon offerings. Unlike eFlash, which is built down into the silicon, eMRAM’s magnetic element is built up in the metal layers, so it is more easily implemented into a logic process such as FD-SOI with no impact on FEOL transistors. Additionally, eMRAM’s higher endurance, faster write speed increases SoC performance, and the low write energy reduces power consumption by more than 80 percent (vs. 28nm bulk silicon with eFlash).

In particular, GF’s industry leading 22FDX eMRAM platform provides excellent scaling, outstanding RF IP, ultra-low leakage, power island control – and (finally!), eMRAM macros with either eFlash or SRAM interfaces. For the first time, the versatility of GF’s 22FDX eMRAM enables ultra-efficient memory subsystems that power cycle with no time or energy penalty, making it suitable for a broad spectrum of applications.

eMRAM is finally here; ready for SoC designers to take advantage of the superior performance and technology maturity, with GF’s 22FDX eMRAM delivering excellent reliability and manufacturability.

Design your Killer Product today, using GF’s 22FDX “Killer Combo”!

To test drive GF’s 22FDX and embedded memory offerings:

• GF’s Embedded Memory Technology Brief
• GF’s VLSI Symposium Technical paper on eMRAM for GP-MCU Applications
• GF’s IMW Technical paper on eFlash for Automotive MCUs
• GF’s 22FDX Technology Brief

About Author

Dave Eggleston

Dave Eggleston is the Vice President of Embedded Memory at GlobalFoundries, which he joined in 2015. Dave has responsibility for the embedded volatile and non-volatile memory businesses at GlobalFoundries, as well as the related strategic direction and initiatives. Dave is the former CEO and President of Unity Semiconductor, a RRAM industry pioneer acquired by Rambus. He has held technical executive management roles at Rambus, Micron (where he built and spearheaded the NAND systems engineering organization), SanDisk, and AMD. He holds 28 patents in NAND flash and next-generation ReRAM memory, storage system usage, and high volume manufacturing. He currently serves on the Board of Directors of two NVM start-up companies. He received his MSEE from Santa Clara University and his BSEE from Duke University.

By: Dave Lammers​

In all my years as a tech journalist, I’ve rarely been witness to a story as interesting as what is happening in the automotive sector. What could be more fascinating than the race to move beyond today’s gas-powered cars with all-too-human drivers at the wheel?

Will young people, the so-called Generation X drivers, embrace autonomous driving and EVs? Will the concerns about safety, pollution and natural resources contribute to the push for EVs and the ADAS technologies?

And yes, national governments are all competing to make sure that their domestic automotive industries take a pole position.

GF has a lot going for it in automotive. When I moved to Austin in 1998 and started covering Motorola’s automotive semiconductors, I found managers very positive about the support from Chartered Semiconductor Manufacturing Ltd., now a part of GF. And having a fab in Dresden, located nearby Europe’s leading automotive OEMs, is another plus.

To capitalize on its advantages, GF is packaging them together in a new automotive-focused platform, AutoPro™. The goal is to make sure customers have all of the foundry’s automotive technology solutions and manufacturing services available under one roof, enabling customers to quickly obtain quality certifications and minimize their time-to-market.

There is little doubt that the efforts to develop ADAS and EV technologies are fast moving. Mark Granger, vice president of Automotive Product Line Management at GF, predicted at GTC 2017 that by 2020 there will be “a couple hundred thousand fully autonomous cars” on the road.

“Over the next 10, 20, 30 years, autonomous cars have the chance to really save lives, and provide mobility for older drivers. Statistically the loss of life around the world (from auto accidents) is equivalent to losing a 747 (load of passengers) a week. That is a staggering statistic. If we can resolve the ADAS safety challenges, we will be doing something for the world.”

To get there, Granger presented a long list of technology challenges, ranging from lidar to image processing to automotive-use 5G. And on top of ADAS, he noted the advances in electric vehicles that are likely to come in parallel.

Automotive, Granger said, represents a “slew of opportunities, including sensors around the car, so the car can see and understand and react to the world around it. A car will become a data center on wheels. And much of that processing capability will be located in the car, because no one wants to be in a car that depends on a (wireless) link to drive, even in a parking garage.”

Sanjay Jha, the CEO of GF, spoke about the demands that ADAS systems place on the sensors, radar and ICs to engage in “real-time management.”

Noting that a car traveling at 70 mph, or 100 feet per second, must be able to see obstacles, make a decision, and engage the brakes, all within a distance of 100 feet, Jha said the ADAS systems must be able to do “an enormous amount of computation within a millisecond.”

An ADAS-enabled car will include sonar and as many as 16 cameras per car. “The car must be able to take braking action while taking in data from the cameras. It will drive consumption of square kilometers of silicon in the industry, and bring in changes from Von Neumann architectures to distributed computing. This will be a huge and powerful driver for the semiconductor industry.”

22FDX® technology is aimed squarely at these ADAS-enabled cars, with Fab 1in Dresden, Germany and, later, Fab 11 in Chengdu, China positioned to supply automotive-use ICs.

Granger noted that for automotive lidar, GF is working with customers on both silicon germanium- and CMOS-based lidar solutions. “We are working in Fab 1 on 22FDX and SiGe for long-range radar, 40nm CMOS or 22 FDX for short-range, and 28nm or 22nm for camera sensors. The controllers for power windows and others are on our mature nodes, and of course, with the advanced nodes we support the very hefty processing elements that will go into cars for centralized control.”

Overall, the total available market (TAM) for automotive ICs will grow from $35 billion now to $54 billion by 2023. The ADAS content will grow by a 20 percent CAGR, driven by sensors and processing power, while analog and power still retain a majority of the market.

“GF has a wide range of capabilities and can serve every one of these markets,” Granger said.

It will be interesting to watch the role played by China, a nation with a major air pollution problem. China’s government is steering urban consumer toward EVs by reducing taxes and easing the difficult bureaucratic path to getting a car license.

The race is on to see which companies, and which countries, will take the lead in tomorrow’s connected car market. With GF’s experience at its major fab sites, its diversity of technologies, and the new AutoPro platform, it appears to have the right tools to help customers win this most exciting competition.

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.

By: Dave Lammers​

When I was flying west to attend the 2017 GLOBALFOUNDRIES Technology Conference, I couldn’t help but think of a trip 10 years earlier, to the 2007 SEMICON West. In the press room there, tech journalist Katherine Derbyshire showed off her brand-new iPhone, and several of us huddled around watching her double-tap, type on the screen, and perform feats of wizardry that were beyond those of us that had mere Blackberries.

For several years now, we’ve all been thinking about the future of technology. Will people really turn over their wheels to ADAS cars? Will neural networks learn complex tasks? Will augmented reality become so adept that doctors can offer better diagnoses? And will these capabilities run over 5G wireless networks that run circles around today’s links?

There were some answers at the 2017 GTC event in Santa Clara.

Just as the 4G wireless rollout delivered users the fast access to the Web that propelled so many new mobile applications – think Uber and others – the still-developing 5G networks will be needed to provide the performance required to spur autonomous driving, cloud-based applications, smart cities, and a host of others.

GF’s CEO, Sanjay Jha said, “5G is set to transform all industries, and our customers are already gearing up for the future.”

The moniker “5G” will evolve over time, starting out with gigabit-capable versions of the 4G LTE standard and then offering fixed-point and mobile capabilities that go beyond the long-term extension (LTE) roadmap. Jha mentioned the ability to go from today’s megabits-per-second of sustained wireless bandwidth to gigabits-per-second rates, at sub-5 nanosecond latencies.

To get there, GF will offer enhanced versions of its RF SOI, SiGe, and FDX technologies. And behind these networks will be new power solutions based on the BCD and BCD Lite offerings.

Bami Bastani, senior vice president of the RF business unit, said the 5G networks will need to support two segments, one in the sub-6 GHz realm and a millimeter wave segment that operates at 28 GHz and higher. The 5G networks will include picocells in urban areas for point-to-point transfers, and, eventually, mobile networks with enough robustness to support tomorrow’s automobiles. As 5G networks grapple with millimeter waves, Bastani said “the level of integration increases, and the demands increase on linearity and robustness.”

Cristiano Amon, executive vice president of Qualcomm, noted how whole new industries developed, based on the widespread Internet connectivity that the 4G networks supported over the last decade. “The digital economy came of age with the smartphone,” Amon said, and with future economics gains to come from 5G networks, companies such as Qualcomm are “investing heavily” in solving the design challenges that 5G represents.

Amon predicted that 5G capabilities would “enter into the PC space, with no separation between the PC and the mobile space.” And he sees China playing a very important part of Qualcomm’s efforts: “There is so much excitement in China in mobile handsets and in advancing the industry to 5G. Partnering with China has been a very important part of Qualcomm’s success,” he said.

Ten years from now, as technologists fly to the 2027 GTC event, is there anyone who seriously doubts they will be riding to the venue in ADAS-enabled cars, surfing the Web on 5G-enabled phones, and learning about the newest technologies on augmented-reality systems?

All of these things will take time. And patience, by the way, was another noteworthy theme of GTC 2017. Foundries take time to develop, both in terms of technology and their ability to offer EDA tools and IP, to meet customer deadlines and ensure quality.

GTC 2017 was in effect a statement that GF has matured into a reliable manufacturing partner. In 2017, as AMD’s chief technology officer and senior vice president Mark Papermaster said at the GTC event, AMD has seen great success with a newly designed lineup of processors and graphics solutions, created in a partnership with the 14nm FinFET technology ramped successfully at GF’s Malta, N.Y. fab.

And executives from Skyworks and Qorvo also took the stage at GTC 2017 to say that they have succeeded by partnering with GF in the wireless space as well.

Those success stories are good indicators that future successes are in store, for GF and for all of us.

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.

By: Shankaran Janardhanan​

The world’s first mainstream RF SOI foundry platform manufactured on 300mm wafers offers an unmatched combination of best-in-class performance, cost effectiveness and flexibility

GF recently announced some exciting news for designers of RF front end modules. At our flagship annual technology conference, GTC, we unveiled a 300mm RF SOI platform for 4G LTE and sub-6 GHz mobile/wireless applications, which we are calling 8SW.

It offers impressive technical specifications and gives our customers unbeatable economic and time-to-market advantages.

But actually, those aren’t its only noteworthy features. What’s also noteworthy is the fact that it is a tangible result of something intangible by nature but vitally important nonetheless – the unique relationships, mutual respect and deep trust we and our customers share. In a nutshell, we couldn’t have developed it without the support and close working relationships we have with our customers.

With the acquisition of IBM’s Microelectronics business, GF not only gained deep technical knowledge in RF but it has fostered and built upon a legacy of customer intimacy. The result is a new chip-manufacturing technology with a comprehensive set of advanced features that gives customers exactly what they need the most.

Our new 8SW RF-SOI platform provides an unparalleled combination of best-in-class performance, cost effectiveness and the flexibility needed to build chips for the complex front-end modules (FEMs) required by rapidly evolving mobile/wireless communication applications.

It’s not only the best combination of switching, LNA (low-noise amplifier) and logic capabilities on the market, but as a 300mm RF SOI process it uses larger wafers and more sophisticated tooling, bringing compelling economic, design and time-to-market advantages. It also features all-copper interconnect for more current-carrying capacity and efficiency.

The new 8SW platform features switching speeds of sub 85fs, which is about 25 percent faster than our existing 200mm RF-SOI process. For LNAs, it offers peak fMAX of more than 250GHz. Logic circuitry is extremely dense and can operate at either 1.2V or 1.8V, with a power reduction of more than 70 percent versus the previous platform.

Source: Adapted from The5th Generation Mobile Wireless Networks

In addition, overall die size can be as much as 20 percent smaller. Combined with the fact that 300mm wafers are larger and yield more chips, the result is that the new 8SW process enables much more cost-efficient and faster design/development cycles because there is more wafer area available to use for test sites, design variations and multiple simultaneous projects. Time-to-market is also increased because 300mm production tools reduce variability by more than 30 percent versus the 200mm process.

Working Closely With Customers

In developing the 8SW RF SOI platform, we’ve taken dual product- and customer-centric approaches. We worked closely with customers because we needed to understand their detailed knowledge of application requirements as we developed the 8SW platform.

One example of this approach was our recognition of the need to focus our development efforts on continuously improving LNA performance as signals come out of transceiver and move into the front end modules. This focus was a direct result of our close work with customer design teams to ensure the 8SW platform would meet rapidly developing advanced 4G LTE requirements.

The new 8SW platform is manufactured at GF’s 300mm production line in East Fishkill, NY, providing customers with ample capacity because it leverages a partially-depleted SOI technology base that has been in high-volume production since 2008.

By: Dave Lammers​

Faced with bandwidth issues, networking companies are turning to interposers, HBM2 DRAM and leading-edge ASIC technology.

When the big networking companies began developing a new class of terabit routers, they reached what Bob Wheeler, networking analyst at The Linley Group, calls “the breaking point.”

These companies — Cisco, Juniper, Nokia, and others — had been watching the pin counts on their router ASICs “explode” as they worked to get enough bandwidth from commodity DDR DRAMs, mounted on laminate printed circuit boards.

Networking customers are now able to use a new 14nm ASIC (FX-14™) solution from GLOBALFOUNDRIES® which offers connections to High-Bandwidth Memory (HBM2) mounted on a silicon interposer. Rambus Inc. (Sunnyvale) and GF engineers cooperated to bring a Rambus PHY to the FX-14 ASIC platform that provides an impressive 2 terabits per second (Tb/s) of bandwidth.

“This is a solution to a problem we’ve seen coming, which is the inability of external memory to keep up with the bandwidth requirements on the buffers of these ASICs,” Wheeler said. “People tried to use commodity DRAM as long as they could, but because of the pin count explosion, that reached a breaking point.”

The market for communications ASICs is roughly a billion dollars, Wheeler said, noting that routers are expensive systems that can support the cost of an interposer-based (2.5D) solution to get the bandwidth required for high-speed packet buffering.

For the incumbent — DDR-type DRAM running on a laminate PCB — Wheeler said “the big problem from the ASIC perspective was the pin count. You could end up with 2,000-plus-pin devices. The beauty of HBM is that it has a wide interface and stays in the package, so you don’t have to go to a serial interface.”

Markets Beyond Networking? 

Depending how well costs can be improved, the 2.5D (interposer-based) solutions could find other applications in data processing, high-end graphics, self-driving cars, artificial intelligence, and other bandwidth-hungry solutions, said Dave McCann, vice president of packaging R&D and business technical operations at GLOBALFOUNDRIES.

Moving to an interposer brings an enormous improvement in the routing density. For laminate PCB-based solutions, lines and spaces were at 12 microns, but that wiring density often was not achieved because the vertical 50-micron vias between the layers had to be avoided, or routed around, wasting a huge amount of space. With a silicon interposer, the lines and spaces are essentially the same as the back-end of a logic chip, currently about 0.8 microns, said Walter Kocon, a senior manager of technology development at GF.

Using logic-like wiring for routing between the PHY and the HBM2 memory on an interposer involves using fab-level tools, including lithography. Because the interposers are much larger than conventional chips, multiple fields must be stitched together. But Kocon said today’s steppers are very good at switching between reticles, and progress is being made in creating ever-larger interposers.

These fab processing tools are more expensive than conventional laminate-processing tools, but the payback is a massive number of on-chip I/Os (roughly 1,700) between the PHY and the HBM2 memory. And as McCann noted, by keeping the traces very short, power consumption is kept under control compared with the laminate-based serial interfaces used to date.

No Keep Out Area

“With vias enabled by wafer fab technology (<1 micron) in silicon interposers, multiple layers of 0.8-micron lines and spaces can be utilized, because there is essentially no keep out area for the vias. That compares with the conventional PCBs, where routing had to come down from the ASIC and over to the DIMM card, consuming both power and time,” McCann said. With interposer-based interconnect being orders of magnitude smaller, and devices only hundreds of microns apart, the massively parallel routing density supports multi-terabit levels of bandwidth.

But there are manufacturing challenges associated with interposers. “These are big interposers and big ASICs. First, we have to create an interface between the ASIC and the interposer.  Matched expansion properties of the ASIC and silicon interposer are one key to a non-stressed interface.  Design and assembly processes that control warpage are critical. Then spreading the stress between the interposer and the laminate below is critical, because there is a big mismatch at that interface,” McCann said.

Controlling warpage is key to getting good interconnect yields with 2.5D. With very close spacing between the interposer and the ASIC and a bump height of about 70 microns. “This means there is very little tolerance for warpage,” McCann said. Solder that is pushed together, or pulled in the opposite direction, creates connection issues. “We need manufacturing processes to keep all of these surfaces flat, and we believe, along with our OSAT partners, that we can do that,” McCann said.

PHY Cooperation

The PHY was another technical challenge, one that Rambus tackled along with GF. Frank Ferro, senior director of product marketing at Rambus, explained that an HBM2 PHY is a mixed signal function that must be designed very specifically to each process node.

“We do a significant of amount channel modeling and then designed the PHY to meet those channel requirements. And it was a collaboration. We had many discussions over the whole process to ensure a robust design. From Day One, it worked, and that is a strong testament to the Rambus (modeling and signal integrity) tools and the engineers who have a history of designing these PHYs.”

DDR DRAMs support 72 bits of bandwidth, compared with 1,024 for HBM2. With 1,024 bits, controlling the signal integrity is challenging, and Ferro tipped his cap to the GF engineers, many of whom brought experience with high-speed signaling from their days at IBM’s Microelectronics Group.

Asked if he thought 2.5D solutions would spread throughout the high-performance part of the industry, Ferro said it depends on manufacturing yields, and bringing down the cost of the HBM2 DRAM. “2.5D needs to be proven out with high-volume manufacturing. It is a fairly big piece of silicon, and you have to really control warpage.”

Tad Wilder, a principal member of the technical staff at GF, said the 2 terabits-per-second of bandwidth “is quite an impressive amount of bandwidth for a single core. And with the ability to place up to four HBM2 PHYs on a chip, this gives ASIC designers an unprecedented eight terabits-per-second of low power, low latency DRAM access to work with.” He added that the 14nm HBM PHY “Is the largest core we’ve produced for an ASIC, with 15,000 internal pins talking to the Memory Controller and 1,700 external pins talking to the base die of the DRAM stack across the interposer.”

Each DRAM stack contains a base die, which communicates with the ASIC’s HBM2 PHY and up to eight stacked DRAM die above, through thousands of vertical Through Silicon Vias (TSVs).   The total memory per HBM DRAM stack is up to 32GB. To mitigate the noise of more than 1,000 I/O possibly switching, the ASIC HBM2 PHY can take advantage of the complete independence of the eight 128 bit channels by skewing the timing of each channel with respect to another.

Linley Group analyst Wheeler sees momentum building for the HBM2 standard. While Hynix was the initial backer, Wheeler said Samsung has come on strong with its own HBM2 parts. Because so much of the total solution cost is wrapped up in the cost of the HBM2 memories, competition among multiple HBM2 vendors will help drive volumes, reduce costs and improve performance.

Asked if he thought 2.5D solutions would proliferate, McCann said “it is a really great technology that has come of age, with significant revenues. The question is: can we drive down the cost to get it to the next level of volume?”

About Author

Dave Lammers

Dave Lammers is a contributing writer for Solid State Technology and a contributing blogger for GF’s Foundry Files. Dave started writing about the semiconductor industry while working at the Associated Press Tokyo bureau in the early 1980s, a time of rapid growth for the industry. He joined E.E. Times in 1985, covering Japan, Korea, and Taiwan for the next 14 years while based in Tokyo. In 1998 Dave, his wife Mieko, and their four children moved to Austin to set up a Texas bureau for E.E. Times. A graduate of the University of Notre Dame, Dave received a master’s in journalism at the University of Missouri School of Journalism.

By: Gary Dagastine

Since the invention of the transistor, breathtaking advances in semiconductor technology have driven the evolution of computing and communications along a path from centralized mainframes and minicomputers, to networked PCs, to sophisticated mobile devices that can connect to networks at any time from anywhere.

Yet as impressive as these achievements have been, they represent only the beginning of the contributions semiconductors will make to society. Their real impact is yet to come because while there are already billions of internet-connected devices in the world, a much greater number will be connected globally in the next few years for applications such as autonomous vehicles, the Internet of Things (IoT) and many others.

They will require an extensive infrastructure to connect, transmit, process, act upon and store all of the resulting data. Building an infrastructure that can enable such “connected intelligence” is a huge ongoing task that will require so many semiconductors relying on so many technologies, that it’s fair to say a golden era is dawning for the industry.

That was the perspective given recently by GLOBALFOUNDRIES CEO Sanjay Jha and Sr. Vice President and General Manager of Fab 8 Tom Caulfield, in keynote talks at the Mobile World Congress Shanghai and SEMICON West trade shows, respectively.

Their talks were focused on describing this new era of connected intelligence, how it is changing the requirements and conditions for success in the foundry segment, and how GF is making it possible.

Jha spoke about how the explosion of data is leading to a  connected intelligence inter-relationship among data centers, networks and client devices (i.e., smartphones, IoT devices, etc.). He described how GF is in a leadership position to enable it, both with regard to GF’s suite of leading-edge technologies and in terms of the company’s business strategies, such as the building of a new 300mm fab in Chengdu, China for 22FDX®-based products.

“The last 10 years in this industry have probably been the most transformative in our lives,” he said. “One example is that our phones have become an extension of our minds. Another, from a social perspective, is that Facebook now has almost 2 billion monthly users. Considering that China has about 1.4 billion people, the Facebook community is now larger than any other.”

At MWC Shanghai, CEO Sanjay Jha was a keynote speaker and part of a panel speaking on the topic of “Industry & The Human Element”

“I believe the next 10 years is going to be a golden era for the foundry business,” he said. “Industry estimates suggest that by 2025 we will be using 163 zettabytes of data (one zettabyte = 250 billion DVDs). We are collecting, transporting and analyzing all of this information – both at the edge with client devices for real-time decision-making and in the data center for longer-term insight gathering. Semiconductors are the enabling technology.”

Jha believes this transformation is changing the conditions for success in the semiconductor industry – both in terms of technologies and customer engagement models.

Regarding technologies, he described how GF’s dual roadmap of FDX™ technology for battery-powered devices and FinFET technology for high-performance processing in data centers and high-end computing devices is unique, and allows the company to match the right technology with the right application.

When coupled with the company’s legacy of leadership in RF, its new silicon photonics technologies for connectivity, and differentiated ASIC and analog/power technologies, GF is in a unique position to drive progress across the full breadth of new applications in the years ahead.

Regarding engagement models, Jha used China as an example, saying that, “The country is moving from a ‘Made in China’ stage of industry to an ‘Innovated in China’ position, and our Chengdu fab is a strategic, long-term joint venture partnership with the Chengdu government that is conceived in that light. It will be central to our IoT and 5G technologies, and when complete it will be the largest fab in China, with a building half a kilometer long.” Click here to view Sanjay Jha’s presentation.

At SEMICON West, Caulfield said that ever since Gordon Moore’s famous observations known as Moore’s Law were made some 50 years ago, the industry has been putting the pieces into place for what comes next, in effect. “We’ve made products that are smart, and that’s great, but now we’re going to take ‘smart’ and do something special with it. We are moving beyond an internet of smart things, to a framework of ‘connected intelligence’ whose operation and capabilities in many ways mimic the way the mind works.”

Tom Caulfield, SVP & GM of Fab 8, was a keynote speaker and a part of the opening ceremony for SEMICON West 2017

Caulfield noted that the engine powering this move is semiconductor innovation but that in order to keep achieving the technological progress predicted by Moore’s Law, the industry must operate differently because things have become so complex and inter-twined. Scaling is still critical, but scaling alone is no longer an effective strategy.

“After 50 years the game is still ahead of us. We must redefine innovation, collaborate differently and shift engagement behaviors in order to drive needed innovation in data analysis, bandwidth, storage density and power management,” he said. He pointed to GF’s dual-technology roadmap as an example of how innovation is being redefined, with FinFETs representing one path forward for high-performance computing and FDX representing another path forward for wireless, battery-powered devices.

With regard to collaborating differently, Caulfield noted that as the world has developed and the industry has grown and become more complex, old ways of doing business are no longer adequate. He said that a strategy of collaboration today needs to be built on three elements: strategic partnerships with key suppliers; “coopetition” with industry rivals, meaning to cooperate with them in some areas and compete with them in others; and public-private partnerships.

He used the Albany Nanotech research facility as an example of the benefits of coopetition, saying, ”For the industry, it offsets our collective expense to develop technology at the leading edge and lets us build scale in key technologies on a virtual basis.”

With regard to engagement behaviors, he said, “The industry is now so complex that we’ve reached the point where when you look at a project team it’s difficult to know who is the vendor and who is the customer.  Sure, everyone has a boss, but they are really dedicated to the project.”

That’s just one example of how engagement behavior needs to evolve, Caulfield said. “Sharing ideas across global teams, working in an interdisciplinary fashion and encouraging a diversity of ideas are absolutely vital to technical innovation in today’s world,” he said. Click here to view Tom Caulfield’s presentation.

About Author

Gary Dagastine

Gary Dagastine is a writer who has covered the semiconductor industry for EE Times, Electronics Weekly and many specialized media outlets. He is a contributing editor at Nanochip Fab Solutions magazine and also is the Director of Media Relations for the IEEE International Electron Devices Meeting (IEDM), the world’s most influential technology conference for semiconductors. He started in the industry at General Electric Co. where he provided communications support to GE’s power, analog and custom IC businesses. Gary is a graduate of Union College in Schenectady, New York,

By: Gerd Teepe​

Recently, Cadence hosted its two-day European CDNLive event at a multi-purpose arena in Munich. The arena at the INFINITY Hotel & Conference Resort is also often a draw for ice-hockey tournaments, rock concerts and other high-profile events and visitors. In fact, the Bayern-Munich soccer team has gathered here before important games the last couple of years, bringing further glamour to the area.

While the Bayern Munich players did not occupy the arena this year, there was another star attraction at the show—a technical innovation heralding a new era in image processing. Dream Chip Technologies GmbH of Hannover, Germany demonstrated a system with an image processing chip designed and manufactured with GLOBALFOUNDRIES’ 22nm FD-SOI (22FDX®) technology.

Dream Chip’s ADAS SoC system platform is based on a quad ARM® A53 processor complemented with a dual ARM-R5 lock-step processor, making the chip suitable for enhanced ASIL-type security applications. The image workhorse of the chip is the Vision-P6 processor from Cadence.

Source Dream Chip: Full system architecture of the image processing platform, soon to be implemented by Dream Chip.

The Vision P6 architecture from Cadence is based on the Tensilica architecture and is targeted for Convolutional Neural Network computations (CNNs). Image objects are detected by correlation of video images with a database of known images. For applications in the car, like sign- and pedestrian-recognition, this application needs to run at real-time with 30 frames per second. In essence, it’s a massive computational comparison of pictures occurring in real-time.

The prototype shown at CDNLive is the first-ever live system with an SoC implemented with GF’s 22FDX technology.  The chip is 64mm2 and is mounted on a package substrate together with two LPDDR4 memories.

Source Dream Chip: System module with chip and two LPDDR4-memories

The Dream Chip ADAS chip is a complex and multifunctional SoC. At CDNlive, Dream Chip demonstrated video capabilities through a system board mounted on top of a model car, with the signal of a hood-mounted GoPro camera fed into the system board.

Jens Benndorf, COO of Dream Chip, explained the further signaling path: “First fed into the chip, the video signal is passed to one of the four IVPs running a filter algorithm, then passed to the video-output and on to the display. It demonstrated that the IVP6 is working.”

 
Source GF: Dream Chip live Demo setup at CDNLive EMEA

In addition to the demo, Benndorf and his team gave a number of presentations on the system, the chip architecture and the CNN-based image processing for which the chip is targeted in the near future.

Dream Chip, GF, and partners are working fast and furious (pun intended!) to accelerate the SoC prototype for production readiness. First silicon was demonstrated in February 2017 at Mobile World Congress in Barcelona, and a video on the platform was showcased at CDNLive in May. What will be next? Ride with us, and find out!  22FDX is enabling innovation in ADAS applications and eventually will for autonomous driving too. By then, Bayern Munich players will certainly notice.